Quectel SG368Z Series Hardware Design page 71

⚫ 1 group of 1-lane PCIe 2.0 interface
⚫ Only supports RC mode
⚫ PCIE1_REFCLK_P/M can support both output and input, but they output clock signals for EP device
by default.
⚫ PCIe1 data channel can be multiplexed into SATA2 or
multiplexing relationship, see document [2].
PCIe2 Interface:
⚫ 1 group of 2-lane PCIe 3.0 interface
⚫ Supports PCIe 3.0 × 2 lane RC mode, compatible with PCIe 3.0 × 1 lane RC mode;
PCIe 3.0 × 1 lane RC mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel
⚫ Supports PCIe 3.0 × 2 lane EP mode, compatible with PCIe 3.0 × 1 lane EP mode;
PCIe 3.0 × 1 lane EP mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel
⚫ Supports PCIe 3.0 × 1 lane RC mode + PCIe 3.0 × 1 lane RC mode
⚫ PCIE2_REFCLK_P/M only support input:
Need to provide HCSL level clock input;
Must meet the requirements for PCIe 3.0 clock.
Table 30: Pins Description of PCIe Interfaces
Pin Name
PCIE1_TX_P
PCIE1_TX_M
PCIE1_RX_P
PCIE1_RX_M
PCIE1_REFCLK_P
PCIE1_REFCLK_M
PCIE1_CLKREQ_N
PCIE1_WAKE_N
PCIE1_RST_N
PCIE2_TX0_P
PCIE2_TX0_M
PCIE2_TX1_P
SG368Z_Series_Hardware_Design
Pin No. I/O Description
90 AO PCIe1 transmit (+)
91 AO PCIe1 transmit (-)
86 AI PCIe1 receive (+)
87 AI PCIe1 receive (-)
81 AO PCIe1 reference clock (+)
82 AO PCIe1 reference clock (-)
366 DI PCIe1 clock request
367 DI PCIe1 wake up
333 DO PCIe1 reset
58 AO PCIe2 transmit 0 (+)
54 AO PCIe2 transmit 0 (-)
63 AO PCIe2 transmit 1 (+)
Smart Module Series
QSGMII/SGMII* interface. For detailed
Comment
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