Clearing Assignments - Paradyne FrameSaver SLV 9124 User Manual

Clearing Assignments

9124-A2-GB20-00
Table 3-7. Signaling and Trunk Conditioning Values (3 of 3)
Network Side Meaning
FXSD-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXSDN interface (ABCD = 1111).
PLAR3idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
a PLAR D3 interface (ABCD = 0000).
PLAR3busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an PLAR D3 interface (ABCD = 1111).
PLAR4idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
a PLAR D4 interface (ABCD = 1111).
PLAR4busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an PLAR D4 interface (ABCD = 0000).
DPO-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
a DPO interface (ABCD = 0000).
DPO-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for a DPO interface (ABCD = 1111).
DPT-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
a DPT interface (ABCD = 0000).
DPT-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for a DPT interface (ABCD = 1111).
USER- xxxx The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent a user-defined
pattern of ABCD = xxxx .
1
xxxx is the same value on both the Network and the DSX-1 sides.
Clearing assignments sets all time slots to Unassgn (unassigned).
Main Menu Configuration
March 2000
Time Slot Assignment
Configuration
DSX-1 Side
FXOD-busy
PLAR3idle
PLAR3busy
PLAR4idle
PLAR4busy
DPT-idle
DPT-busy
DPO-idle
DPO-busy
1
USER- xxxx
Clear Assignments
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