Paradyne FrameSaver SLV 9124 User Manual page 66

Configuration
3-38
Table 3-7. Signaling and Trunk Conditioning Values (2 of 3)
Network Side Meaning
E&M-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an E&M interface (ABCD = 0000).
E&M-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an E&M interface (ABCD = 1111).
FXOg-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXO Ground-Start interface (ABCD = 1111).
FXOg-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXO Ground-Start interface (ABCD = 0101).
FXOl-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXO Loop-Start interface (ABCD = 0101).
FXOl-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXO Loop-Start interface (ABCD = 0101).
FXSg-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXS Ground-Start interface (ABCD = 0101).
FXSg-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXS Ground-Start interface (ABCD = 1111).
FXSl-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXS Loop-Start interface (ABCD = 0101).
FXSl-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXS Loop-Start interface (ABCD = 1111).
FXOD-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXODN interface (ABCD = 0000).
FXOD-busy The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the busy state
for an FXODN interface (ABCD = 1111).
FXSD-idle The signaling bits transmitted to the cross-connected
T1 interface during a CGA represent the idle state for
an FXSDN interface (ABCD = 0000).
March 2000
DSX-1 Side
E&M idle
E&M busy
FXSg-idle
FXSg-busy
FXSl-idle
FXSl-busy
FXOg-idle
FXOg-busy
FXOl-idle
FXOl-busy
FXSD-idle
FXSD-busy
FXOD-idle
9124-A2-GB20-00