Ml310 Pm2 User I/O - Xilinx ML310 User Manual

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Table 2-31: PM1 Pinout (Continued)
F17
F18
F19
F20
Notes:
1. LVDS pairs are shown shaded; all other signals are single-ended.
2. LVDS pairs can also be used as single-ended I/O at 2.5V
3. NC indicates a "no connect" signal.

ML310 PM2 User I/O

The PM2 connector makes most of the LVDS pairs available to the user, along with single-
ended signals.
Table 2-32: PM2 Pinout
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
68
PM1 Pin FPGA Pin
AK11
AK12
AK24
AK25
Table 2-32 shows the pinout for the PM2 connector on the ML310.
PM2 Pin FPGA Pin
T5 IO_L89N_3
T6 IO_L89P_3
T3 IO_L88N_3
T4 IO_L88P_3
V3 IO_L58N_3
V4 IO_L58P_3
U7 IO_L56N_3
U8 IO_L56P_3
V7 IO_L53N_3
V8 IO_L53P_3
AC15 IO_L67P_4
AB15 IO_L67N_4
AA4 IO_L48P_3
AA3 IO_L48N_3
AD2 IO_L42P_3
AD1 IO_L42N_3
AG2 IO_L06P_3
AG1 IO_L06N_3
AH5 IO_L02P_3
AG5 IO_L02N_3
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Chapter 2: ML310 Embedded Development Platform
Pin Description ML310 Schematic Net
RXNPAD18 RXNPAD18_AK11
RXPPAD18 RXPPAD18_AK12
RXNPAD21 RXNPAD21_AK24
RXPPAD21 RXPPAD21_AK25
Pin Description ML310 Schematic Net
PM_IO_69
PM_IO_68
PM_IO_67
PM_IO_66
PM_IO_55
PM_IO_54
PM_IO_51
PM_IO_50
PM_IO_45
PM_IO_44
PM_IO_72
PM_IO_73
PM_IO_34
PM_IO_35
PM_IO_22
PM_IO_23
PM_IO_6
PM_IO_7
PM_IO_0
PM_IO_1
FPGA Bank
V
CCO
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
ML310 User Guide
UG068 (v1.01) August 25, 2004