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Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
ddr_dqs[5]
ddr_dqs[6]
ddr_dqs[7]
ddr_dq[0]
ddr_dq[1]
ddr_dq[2]
ddr_dq[3]
ddr_dq[4]
ddr_dq[5]
ddr_dq[6]
ddr_dq[7]
ddr_dq[8]
ddr_dq[9]
ddr_dq[10]
ddr_dq[11]
ddr_dq[12]
ddr_dq[13]
ddr_dq[14]
ddr_dq[15]
ddr_dq[16]
ddr_dq[17]
ddr_dq[18]
ddr_dq[19]
ddr_dq[20]
ddr_dq[21]
ddr_dq[22]
ddr_dq[23]
ddr_dq[24]
ddr_dq[25]
ddr_dq[26]
ddr_dq[27]
ddr_dq[28]
ddr_dq[29]
ddr_dq[30]
ddr_dq[31]
24
Chapter 2: ML310 Embedded Development Platform
XC2VP30 Pin
(U37)
M29
H29
F29
AG28
AG26
AE26
AD26
AH27
AH26
AF25
AD25
AF28
AD28
AB25
AB26
AF27
AD27
AC25
AC26
AC27
AC28
AA26
Y26
AB27
AB28
AA25
Y27
W28
W25
V27
V25
W27
W26
V28
V26
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Schem Signal Name
DDR_DQS02
DDR_DQS01
DDR_DQS00
DDR_DQ63
DDR_DQ62
DDR_DQ61
DDR_DQ60
DDR_DQ59
DDR_DQ58
DDR_DQ57
DDR_DQ56
DDR_DQ55
DDR_DQ54
DDR_DQ53
DDR_DQ52
DDR_DQ51
DDR_DQ50
DDR_DQ49
DDR_DQ48
DDR_DQ47
DDR_DQ46
DDR_DQ45
DDR_DQ44
DDR_DQ43
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ39
DDR_DQ38
DDR_DQ37
DDR_DQ36
DDR_DQ35
DDR_DQ34
DDR_DQ33
DDR_DQ32
UG068 (v1.01) August 25, 2004
DIMM
(P7)
25
14
5
179
178
175
174
88
87
84
83
171
170
166
165
80
79
73
72
162
161
155
153
69
68
64
61
151
150
147
146
60
57
55
53
ML310 User Guide
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