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The PPC405 JTAG (Joint Test Action Group) Debug port complies with IEEE standard
1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture. This
standard describes a method for accessing internal chip resources using a four-signal or
five-signal interface. The PPC405 JTAG Debug port supports scan-based board testing and
is further enhanced to support the attachment of debug tools. These enhancements comply
with the IEEE 1149.1 specifications for vendor-specific extensions and are compatible with
standard JTAG hardware for boundary-scan system testing.
The PPC405 JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI,
and TDO. It also implements the optional TRST signal. The frequency of the JTAG clock
signal can range from 0 MHz (DC) to one-half of the processor clock frequency. The JTAG
debug port logic is reset at the same time the system is reset, using TRST. When TRST is
asserted, the JTAG TAP controller returns to the test-logic reset state.
Refer to the PPC405 Processor Block Manual for more information on the JTAG debug-port
signals. Information on JTAG is found in the IEEE standard 1149.1-1990.
Figure 2-9
Debug interfaces for high-speed, controlled-impedance signaling. For more information
functions: starting and stopping the processor, single-stepping instruction execution on the
trace-debug capabilities, how trace-debug works, and how to connect an external trace
tool, see the RISCWatch Debugger User's Guide.
3. Virtex-II Pro Platform FPGA Documentation - Volume 2(a): PPC405 User Manual, March 2002 Release, p. 557.
34
Chapter 2: ML310 Embedded Development Platform
shows a 38-pin Mictor connector that combines the CPU Trace and the CPU
GND, G1, G2, G3, G4, G5
038
TRC_TS6
036
TRC_TS5
034
TRC_TS4
032
TRC_TS3
030
TRC_TS2E
028
TRC_TS1E
026
TRC_TS2O
024
TRC_TS1O
022
ATD 16
020
ATD 17
018
2.5V
ATD 18
016
ATD 19
014
TRC_VSENSE
012
010
008
006
TRC_CLK
004
002
Figure 2-9: Combined Trace/Debug Connector Pinout
www.xilinx.com
1-800-255-7778
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MICTOR 38
037
035
033
031
029
027
025
023
021
019
017
015
013
011
009
007
005
003
001
UG068 (v1.01) August 25, 2004
(3)(3)
ATD_8
ATD_9
ATD_10
ATD_11
ATD_12
ATD_13
ATD_14
ATD_15
CPU_TRST_N
CPU_TDI
CPU_TMS
CPU_TCK
CPU_TDO
CPU_HALT_N
UG068_05_20_073004
ML310 User Guide
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