Xilinx ML310 User Manual page 38

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Table 2-10: PCI Controller Connections (Continued)
PCI_INTA
PCI_INTB
PCI_INTC
PCI_INTD
PCI_INTE
PCI_INTF
PCI_REQ0_N
PCI_REQ1_N
PCI_REQ2_N
PCI_REQ3_N
PCI_REQ4_N
PCI_GNT0_N
PCI_GNT1_N
PCI_GNT2_N
PCI_GNT3_N
PCI_GNT4_N
PCI_CBE[0]
PCI_CBE[1]
PCI_CBE[2]
PCI_CBE[3]
PCI_FRAME_N
PCI_IRDY_N
PCI_TRDY_N
PCI_STOP_N
PCI_DEVSEL_N
PCI_PERR_N
PCI_SERR_N
PCI_LOCK
PCI_IDSEL
PCI_REQ64_N*
PCI_ACK64_N*
38
UCF Signal Name
L5
N2
M2
R9
P9
M3
P1
N1
P7
P8
N3
P2
P3
R7
R8
P4
J2
H2
M7
M8
K6
K1
J1
M5
M6
J3
J4
L2
K2
F8
E8
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Chapter 2: ML310 Embedded Development Platform
XC2VP30 Pin (U37)
Description
PCI Interrupt Signals
PCI Request Signals
PCI Grant Signals
PCI Byte Enable Signals
PCI Control Signals
# PM_IO_3V_1
# PM_IO_3V_2
ML310 User Guide
UG068 (v1.01) August 25, 2004

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