Gpio, Connector J5; System Management Bus (Smbus) - Xilinx ML310 User Manual

Board Hardware

GPIO, connector J5

There are 15 GPIO pins connecting the ALi M1535D+ to the J5 24 pin header. These may be
accessed via the ALi M1535D+ via the PCI Bus. Please review the ALi M1535D+ Data
sheets for more detailed information.
Table 2-17
South Bridge.
Table 2-17: Type of GPIO Available on Header J5
Output
Input
Input/Output
Table 2-18
GPIO header (J5). Please review the ALi M1535D+ Data sheets, located on the ML310
CDROM, for more detailed information.
Table 2-18: GPIO Connections on Header J5
Schem Net Name
GPO_35
GPO_34
GPO_30
GPO_29
GPO_10
GPI_36
GPI_34
GPI_25
GPI_24
GPIO_3
GPIO_23
GPIO_22
GPIO_2
GPIO_1
GPIO_0

System Management Bus (SMBus)

The System Management Bus (SMBus) host controller in the M1535D+ supports the ability
to communicate with power related devices using the SMBus protocol. It provides quick
ML310 User Guide
UG068 (v1.01) August 25, 2004
shows the types and number of GPIO signals available to the user from the ALi
Number
ALi GPIO Types
Available
5
4
6
shows the connections from the ALi, M1535D+, GPIO signals available at the
GPIO Header
(J5)
24
22
20
23
21
7
5
3
1
15
19
17
13
11
9
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M1535D+
IO Type
(U15)
P19 Output
P18 Output
N18 Output
N17 Output
T3 Output
U8 Input
W7 Input
E9 Input
M17 Input
Y4 Input/Output
U5 Input/Output
U6 Input/Output
W4 Input/Output
V4 Input/Output
Y3 Input/Output
R
45