Xilinx ML310 User Manual page 56

R
The front panel interface provides the following status information available at the J23
header.
Table 2-25
Table 2-25: Front Panel Interface connector, J23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
56
♦
FPGA Configuration DONE
- Output intended for driving an LED
♦
IDE Disk access
- Output intended for driving an LED
♦
ATX Power
Output intended for driving an LED
-
♦
2 FPGA User Defined Signals
- Outputs intended for driving LEDs
♦
ATX Speaker
- Output, see Ali M1535D+ data sheet for more details
♦
Keyboard Inhibit (active low input)
shows the signals available at the Front Panel Interface header, J23.
J23
Schem Signal
Pin
SYACE_CFGA0
FPGA_USER_LED1
SYACE_CFGA1
FPGA_USER_LED2
SYACE_CFGA2
NC
LED_DONE_R
GND
ATX_PWRLED
ATX_SPKR
NC
NC
GND
GND
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Chapter 2: ML310 Embedded Development Platform
Description
Used to select System ACE configuration,
CFGADDR0
User Defined function, Connects to XC2VP30, U37-
AH10, (2.5V Bank)
Used to select System ACE configuration,
CFGADDR1
User Defined function, Connects to XC2VP30, U37-
AC14, (2.5V Bank)
Used to select System ACE configuration,
CFGADDR2
No Connect
Remote FPGA DONE indicator, Tie this pin to Anode
of user's LED and Cathode to GND
Ground
ATX 3.3V power indicator, Tie this pin to Anode of
user's LED and Cathode to GND
Used to drive user defined ATX Speaker input
No Connect
No Connect
Ground
Ground
ML310 User Guide
UG068 (v1.01) August 25, 2004