Xilinx ML310 User Manual page 70

R
Table 2-32: PM2 Pinout (Continued)
D14
D15
D16
D17
D18
D19
D20
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
Notes:
1. LVDS pairs are shown shaded; all other signals are single-ended.
2. LVDS pairs can also be used as single-ended I/O at 2.5V
3. NC indicates a "no connect" signal.
70
PM2 Pin FPGA Pin
AA5 IO_L44N_3
AC4 IO_L43P_3
AC3 IO_L43N_3
AE4 IO_L33P_3
AE3 IO_L33N_3
AF4 IO_L34P_3
AF3 IO_L34N_3
AA1 IO_L51N_3
AB1 IO_L51P_3
U2 IO_L87N_3
U3 IO_L87P_3
Y2 IO_L54N_3
AA2 IO_L54P_3
Y4 IO_L49N_3
Y5 IO_L49P_3
NC NC
AG15 IO_L74P_4
W8 IO_L47P_3
W7 IO_L47N_3
AB4 IO_L46P_3
AB3 IO_L46N_3
AE2 IO_L39P_3
AE1 IO_L39N_3
AH2 IO_L03P_3
AH1 IO_L03N_3
AD4 IO_L37P_3
AD3 IO_L37N_3
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Chapter 2: ML310 Embedded Development Platform
Pin Description ML310 Schematic Net
PM_IO_27
PM_IO_24
PM_IO_25
PM_IO_10
PM_IO_11
PM_IO_12
PM_IO_13
PM_IO_41
PM_IO_40
PM_IO_65
PM_IO_64
PM_IO_47
PM_IO_46
PM_IO_37
PM_IO_36
NC
PM_CLK_BOT
PM_IO_32
PM_IO_33
PM_IO_30
PM_IO_31
PM_IO_18
PM_IO_19
PM_IO_2
PM_IO_3
PM_IO_16
PM_IO_17
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
ML310 User Guide
UG068 (v1.01) August 25, 2004