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Board Hardware
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
ddr_ad[2]
ddr_ad[3]
ddr_ad[4]
ddr_ad[5]
ddr_ad[6]
ddr_ad[7]
ddr_ad[8]
ddr_ad[9]
ddr_ad[10]
ddr_ad[11]
ddr_ad[12]
ddr_ba[0]
ddr_ba[1]
ddr_casb
ddr_cke
ddr_csb
ddr_rasb
ddr_web
ddr_clk
ddr_clkb
ddr_clk_fb
ddr_clk_fb_out
ddr_dm[0]
ddr_dm[1]
ddr_dm[2]
ddr_dm[3]
ddr_dm[4]
ddr_dm[5]
ddr_dm[6]
ddr_dm[7]
ddr_dqs[0]
ddr_dqs[1]
ddr_dqs[2]
ddr_dqs[3]
ddr_dqs[4]
ML310 User Guide
UG068 (v1.01) August 25, 2004
XC2VP30 Pin
(U37)
AG20
AF23
AH22
AF22
AF21
AH21
AG21
AJ21
AK21
AH20
AF20
AG18
AF19
AF17
AG24
AE17
AE16
AD16
V30
U30
AF16
AG25
AH29
AE29
AA24
AB30
P30
M30
K24
E30
AG30
AF30
AA28
Y29
P28
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Schem Signal Name
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_BA0
DDR_BA1
DDR_CAS_N
DDR_CKE0
DDR_S0_N
DDR_RAS_N
DDR_WE_N
DDR_CK0
DDR_CK0_N
DDR_CLK_FB
DDR_CLK_FB
DDR_DQM07
DDR_DQM06
DDR_DQM05
DDR_DQM04
DDR_DQM03
DDR_DQM02
DDR_DQM01
DDR_DQM00
DDR_DQS07
DDR_DQS06
DDR_DQS05
DDR_DQS04
DDR_DQS03
R
DIMM
(P7)
41
130
37
32
125
29
122
27
141
118
115
59
62
65
21
157
154
63
137
138
N/A
N/A
177
169
159
149
129
119
107
97
86
78
67
56
36
23
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