Ml310 Pm2 User I/O - Xilinx ML310 User Manual

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ML310 PM2 User I/O

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Table 2-31: PM1 Pinout (Continued)
PM1 Pin FPGA Pin
F17 AK11
F18 AK12
F19 AK24
F20 AK25
Notes:
1. LVDS pairs are shown shaded; all other signals are single-ended.
2. LVDS pairs can also be used as single-ended I/O at 2.5V
3. NC indicates a "no connect" signal.
The PM2 connector makes most of the LVDS pairs available to the user, along with single-
ended signals. Table 2-32
Table 2-32: PM2 Pinout
PM2 Pin FPGA Pin
A1 T5
A2 T6
A3 T3
A4 T4
A5 V3
A6 V4
A7 U7
A8 U8
A9 V7
A10 V8
A11 AC15
A12 AB15
A13 AA4
A14 AA3
A15 AD2
A16 AD1
A17 AG2
A18 AG1
A19 AH5
A20 AG5
Chapter 2: ML310 Embedded Development Platform
Pin Description ML310 Schematic Net
RXNPAD18 RXNPAD18_AK11
RXPPAD18 RXPPAD18_AK12
RXNPAD21 RXNPAD21_AK24
RXPPAD21 RXPPAD21_AK25
shows the pinout for the PM2 connector on the ML310.
Pin Description
IO_L89N_3 PM_IO_69
IO_L89P_3 PM_IO_68
IO_L88N_3 PM_IO_67
IO_L88P_3 PM_IO_66
IO_L58N_3 PM_IO_55
IO_L58P_3 PM_IO_54
IO_L56N_3 PM_IO_51
IO_L56P_3 PM_IO_50
IO_L53N_3 PM_IO_45
IO_L53P_3 PM_IO_44
IO_L67P_4 PM_IO_72
IO_L67N_4 PM_IO_73
IO_L48P_3 PM_IO_34
IO_L48N_3 PM_IO_35
IO_L42P_3 PM_IO_22
IO_L42N_3 PM_IO_23
IO_L06P_3 PM_IO_6
IO_L06N_3 PM_IO_7
IO_L02P_3 PM_IO_0
IO_L02N_3 PM_IO_1
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ML310 Schematic Net
ML310 User Guide
UG068 (v1.01) August 25, 2004
FPGA Bank
V
CCO
FPGA Bank
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CCO
2.5V
2.5V
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2.5V
2.5V
2.5V
2.5V
2.5V
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