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Xilinx ML40 Series User Manual

Edk processor reference design
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ML40x EDK Processor
Reference Design
User Guide for EDK 8.1
UG082 (v5.0) June 30, 2006
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  • Page 1 ML40x EDK Processor Reference Design User Guide for EDK 8.1 UG082 (v5.0) June 30, 2006...
  • Page 2 Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

  • Page 3: Table Of Contents

    Documentation Provided by Xilinx ........
  • Page 4 Launching Xilinx Platform Studio (XPS) ........
  • Page 5 Control Registers (DCR Interface) ......... . . 79 ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 6 ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 7: Schedule Of Figures

    Figure 8-5: Vertical Data ............77 ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 8 ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 9: Schedule Of Tables

    Table 8-1: Global Signals ............71 ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 10 Table 8-7: Control Registers (DCR Interface) ........79 www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 11: Preface: About This Guide

    To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. ML40x EDK Processor Reference Design www.xilinx.com...

  • Page 12: Conventions

    IOB #2: Name = CLKIN’ Repetitive material that has been omitted Repetitive material that has allow block block_name loc1 Horizontal ellipsis . . . been omitted loc2 ... locn; www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 13: Online Document

    Figure 2-5 in the Virtex-II Red text in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 14 Preface: About This Guide www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 15: Chapter 1: Introduction To The Ml40X Embedded Processor Reference System

    Processor Reference System. • Operating System Requirements: ♦ Windows XP Professional or Linux Note: A PC is required for FPGA download and debug via Xilinx download cables. • Hardware Requirements: ♦ Xilinx ML401, ML402, ML403, or ML405 evaluation platform •...

  • Page 16: Coreconnect

    CoreConnect Download and installation of the IBM CoreConnect Toolkit can be useful for hardware and systems. The CoreConnect Toolkit is only available to CoreConnect licensees. Xilinx has simplified the process of becoming a CoreConnect licensee through Web-based registration available at http://www.xilinx.com/coreconnect. CoreConnect licensees are entitled to full access to the CoreConnect Toolkit including powerful bus functional modeling, bus monitoring tools, and periodic updates.

  • Page 17: Further Reading

    Further Reading Further Reading Xilinx provides a wealth of valuable information to assist you in your design efforts. Some of the relevant documentation is listed below with more information available through the Xilinx Support website at http://www.xilinx.com/support. To obtain the most recent revision of documentation related to the ML40x board, see the corresponding Web page: •...
  • Page 18 Chapter 1: Introduction to the ML40x Embedded Processor Reference System www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 19: Chapter 2: Ml40X Embedded Processor Reference System

    Processor IP Reference Guide (see <EDK Install Directory>/doc/proc_ip_ref_guide.pdf) and in Chapter 4, “Introduction to Hardware Reference IP.” ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 20 I/Os GPIO MEMC Memory UART SRAM Flash OPB2PLB Bridge AC97 Sound Ctlr Memory Mapped Bridge DCR Bus UG082_02_01_050406 Figure 2-1: Hardware View of ML40x Embedded MicroBlaze Reference System www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 21 I/Os MEMC Memory UART PLB2OPB SRAM Bridge Flash AC97 Sound Controller Memory Mapped Bridge DCR Bus UG082_02_02_050406 Figure 2-2: Hardware View of ML40x Embedded PPC405 Reference System ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 22: Processor Local Bus (Plb)

    • PLB Arbiter ♦ 64-bit Xilinx PLB Arbiter In general, all PLB devices are optimized around the FPGA architecture and use pipelining to improve maximum clock frequencies and reduce logic utilization. Refer to the documentation accompanying each device for more information about its design.

  • Page 23: On-Chip Peripheral Bus (Opb)

    8- or 16-bit interfaces or those that require dynamic bus sizing functionality are not directly supported. It is recommended that all new OPB peripherals support byte-enable operations for better performance and reduced logic utilization. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 24: Device Control Register (Dcr)

    PS/2 Port #2 • External USB chip • System ACE MPU • AC97 sound controller (play buffer) • AC97 sound controller (record buffer) • Ethernet PHY • IIC controller (PPC405 system) www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 25: Clock/Reset Distribution

    User IP blocks should be designed to take into account the possible skew in the global reset and still start up properly. Alternatively, the global reset can be registered locally in each IP block to generate a synchronous reset signal. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 26: Cpu Debug Via Jtag

    JTAG chain for CPU debug and FPGA programming is that this simplifies the number of cables needed; a single JTAG cable (like the Xilinx Parallel Cable IV cable) can be used for bitstream download as well as CPU software debugging.

  • Page 27: Synthesis And Implementation

    Embedded Processor Reference System including synthesis, implementation, and software compilation. EDK offers a GUI or command line interface to run these tools as part of the design flow. Consult the EDK documentation for more information. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 28: Memory Map

    FFFE80FF FFFE8000 256 B MicroBlaze systems only Memory-Mapped DCR Device Map Address Comment Device Size (DCR Addr Range) TFT VGA Controller D0000207 D0000200 TFT Control Regs (0x080- 0x081) UG082_02_04_050406 www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 29: Ml40X Specific Registers

    General Purpose DIP Switch 6 (ML401/ML402 only) General Purpose DIP Switch 7 (ML401/ML402 only) General Purpose DIP Switch 8 (ML401/ML402 only) SMA “Input N” (ML401/ML403/ML405 only) SMA “Input P“(ML401/ML403/ML405 only) SMA “Output N“(ML401/ML403/ML405 only) ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 30: Ml40X Control Register 1

    “ML40x Control Register 2,” Bit 12). Reading this bit reads the value from the external pin. A “1” value indicates the CPU reset button was pushed. 31-13 (MSB) Reserved. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 31: Ml40X Control Register 2

    USB Reset. Setting this bit to a 1 resets the USB controller chip. This bit must be set back to 0 to permit normal operation of the USB controller. 31-14 (MSB) Reserved. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 32: Ml40X Character Lcd General Purpose I/O Registers

    J5, Pin 56; J5, Pin 54 13-12 J5, Pin 28; J5, Pin 26 29-28 J5, Pin 60; J5, Pin 58 15-14 J5, Pin 32; J5, Pin 30 31-30 J5, Pin 64; J5, Pin 62 www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 33: Ml40X Single-Ended Expansion Header General Purpose I/O Registers

    J6, Pin 24 J6, Pin 56 J6, Pin 26 J6, Pin 58 J6, Pin 28 J6, Pin 60 J6, Pin 30 J6, Pin 62 J6, Pin 32 J6, Pin 64 ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 34: Extending Or Modifying The Design

    Set its configuration parameters (i.e., base address) in the system.mhs file (or use the Add/Edit Cores feature of the EDK GUI). Add appropriate timing and pinout constraints to the UCF file. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 35: Introduction

    ♦ MicroBlaze: <Reference Design Install Directory>/projects/ml405_emb_ref/ ♦ PPC405: <Reference Design Install Directory>/projects/ml405_emb_ref_ppc/ These are the areas where the EDK Xilinx Microprocessor Project (XMP) files reside after installing the ML40x Embedded Processor Reference System. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 36: Launching Xilinx Platform Studio (Xps)

    Launching Xilinx Platform Studio (XPS) Open the XPS GUI. On a PC, click: Start → Programs →Xilinx Platform Studio. On Linux, source the necessary environment scripts, and launch XPS: $ xps Open XPS project file for the ML40x Embedded Processor Reference System: Click File →Open Project.

  • Page 37: Instructions For Downloading The Design

    Program) After the design is implemented, a bitstream can be generated and downloaded into an FPGA using a program like iMPACT, available with the Xilinx ISE tools. (A PC should be used for this step.) Connect the download cable from a PC to the ML40x board and power on the board.

  • Page 38: Download Using The System Ace Interface

    CompactFlash cards to enable hardware and software programming of the FPGA. More information about the System ACE interface is available from http://www.xilinx.com/systemace. EDK supports the generation of System ACE files to download bitstreams and software applications onto Virtex-4 FPGAs. This is accomplished by concatenating (1) the JTAG commands to download the bitstream with (2) the JTAG commands to download the software program.

  • Page 39: Software

    Reads audio and video files from CompactFlash via slideshow System ACE interface and displays a slideshow sw/standalone/slideshow/ accompanied by music. Program that asks user with which System ACE sysace_rebooter sw/standalone/sysace_rebooter/ configuration to reconfigure. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 40 Prints Hello World! to a USB printer. sw/standalone/usb_printer Implements a webserver that displays ML40x DIP webserver sw/standalone/web_server/ switch settings and controls LEDs. sw/standalone/ml40x/ xrom ML40x board test and diagnostic program. sw/standalone/xrom/ www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 41: Building The Linux Bsp (Ppc405 Systems Only)

    The Linux kernel and the tools to build the Linux kernel are available from MontaVista (http://www.mvista.com). For further information about using Linux with EDK, refer to Xilinx XAPP765: Getting Started with EDK and MontaVista Linux. Patch the Linux kernel for use with the ML40x board: $ cd linux $ ./patch_linux <path to the copy of the MontaVista Linux kernel>...
  • Page 42 Chapter 3: EDK Tutorial and Demonstration www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 43: Chapter 4: Introduction To Hardware Reference Ip

    • Chapter 5, “Using IPIF to Build IP” • Chapter 6, “OPB AC97 Sound Controller” • Chapter 7, “OPB PS/2 Controller (Dual)” • Chapter 8, “PLB TFT LCD Controller” ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 44: Hardware Reference Ip Source Format And Size

    These area numbers represent a full implementation of each IP synthesized with the Xilinx tool XST. It is important to note that when IP is connected together in a system, logic optimizations and resource sharing can further reduce the overall logic count.

  • Page 45: Chapter 5: Using Ipif To Build Ip

    SRAM protocol IPIF is described below. For this sample design, a 32-bit General Purpose I/O (GPIO) device is created. The GPIO allows a CoreConnect master such as the CPU to control a set of external pins using a simple memory-mapped interface. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 46: Sram Protocol Overview Of Ipif

    OPB or PLB bus interface and passes it to the IP, causing the IP to use the same global clock as the bus it is connected to. The SRAM interface protocol used by the IPIF can be described by observing a write and read transaction. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 47: Basic Write Transactions

    Bus2IP_Clk Bus2IP_Addr Valid Valid Bus2IP_SRAM_CE Bus2IP_BE Valid Valid Valid Valid Bus2IP_Data Bus2IP_WrReq Later Ack due to IP response IP2Bus_WrAck UG082_05_02_050406 Figure 5-2: IPIF Simple SRAM Write Cycle ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 48: Basic Read Transactions

    Bus2IP_RdReq / Bus2IP_WrReq signals, since it only takes one clock cycle to read or write the GPIO registers. If more “access time” is www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 49 The CPU can sense the current value of any pin (regardless of its direction) by reading the read register. Driving the direction of the I/O pin is controlled by the contents of the three-state register. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 50: Using Ipif To Connect A Pre-Existent Peripheral To The Bus

    OR gate, a write strobe can be generated for the IP. If this write strobe must be glitch-free, taps 0, 1, 2, and 3 could be used, OR’ed, and fed into a synchronizing register. Xilinx FPGAs are abundantly equipped with flip-flops, so the amount of logic is not an issue.

  • Page 51: Conclusion

    Reference Guide (located in <EDK Install Directory>/doc/proc_ip_ref_guide.pdf) for the latest information and documentation on IPIF cores. New designs should use these IPIF modules, available through EDK. For reference, the earlier version of the IPIF spec is available in Chapter 6 of Xilinx UG057: ML300 EDK Reference Design User Guide.
  • Page 52 Chapter 5: Using IPIF to Build IP www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 53: Chapter 6: Opb Ac97 Sound Controller

    Intel Audio Codec '97 (AC97) Specification http://www.intel.com/technology/computing/audio/index.htm Features • 16-deep FIFO buffer for record and playback data • Capable of generating interrupts when play/record FIFOs reach given fullness thresholds ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 54: Module Port Interface

    Serial Bit Clock from AC97 Codec. Sync Output Frame synchronization signal to AC97 Codec. SData_Out Output Serial Data output to AC97 Codec. SData_In Input Serial Data input from AC97 Codec. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 55 0 = No Interrupt 1 = empty Num Words = 0 2 = halfempty Num Words <= 7 3 = halffull Num Words >= 8 4 = full Num Words = 16 ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 56: Implementation

    The OPB AC97 controller logic automatically handles the process of serializing the left/right playback data and sending it out to the Codec chip when requested. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 57: Memory Map

    Base Address + 4 [16:31] Read 16-bit data sample from record FIFO. Data should be read two at a time to get data from the left channel followed by the right channel. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 58 0 = Playback FIFO not Half Full 1 = Playback FIFO Half Full [31] Playback FIFO Full: (LSB) 0 = Playback FIFO not Full 1 = Playback FIFO Full www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 59 AC97 Control Data Write Register: Contains the data to be written to the control register in the Codec. This register is used in conjunction with the "AC97 Control Address Register" described above. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 60 Chapter 6: OPB AC97 Sound Controller www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 61: Chapter 7: Opb Ps/2 Controller (Dual)

    This module is an On-Chip Peripheral Bus (OPB) slave device that is designed to control two PS/2 devices such as a mouse and keyboard. It utilizes the Xilinx Intellectual Property InterFace (IPIF) to simplify its design. The OPB PS/2 Controller module generates interrupts upon various transmit or receive conditions.

  • Page 62: Module Port Interface

    Input PS/2 Clock In, Port #2 Clkpd2 Output PS/2 Clock Pulldown, Port #2 Input PS/2 Serial Data In, Port #2 Txpd2 Output PS/2 Serial Data Out Pulldown, Port #2 www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 63 Description C_BASEADDR 32-bit base address of PS/2 controller (must be aligned to 8-KB boundary) C_HIGHADDR Upper address boundary, must be set to value of C_BASEADDR + 0x1FFF (8-KB boundary) ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 64: Implementation

    5V PS/2 clock and data signals low. Note that the PS/2 protocol specifies 5V signalling. Therefore, it is necessary to have the proper interface circuitry to prevent over-voltage conditions on the FPGA I/O. Consult the schematics and documentation for the Xilinx ML40x board for an example implementation of a PS/2 port interface circuit.

  • Page 65: Memory Map

    The register definitions are shown in Table 7-5, page 66 (this table spans several pages). Note: The second PS/2 Port has an identical set of control/status registers at an additional offset of 0x1000. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 66 Software can clear this field indirectly is by using the SRST register. Base Address + 8 [0:7] RX received data. (Offset x08) Base Address + 12 [0:7] TX transmission data. (Offset x0c) www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 67 SIE does not receive a PS/2 Clock while a packet is still being transmitted. Software clears this field by writing an '1' into the corresponding interrupt clear register INTCLR.7 (offset x14.7) ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 68 Writing a '1' to this field sets INTM.7. Writing a '0' has no effect. * If software tries to read from INTMSET (offset x18), the value of INTM register is returned. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 69 Writing a '1' to this field clears INTM.7. Writing a '0' has no effect. * If software tries to read from IINTMCLR (offset x1C), the value of INTM (offset x18) is returned. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 70 Chapter 7: OPB PS/2 Controller (Dual) www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 71: Overview

    VGA screen. It is capable of showing up to 256K colors and is designed for a TFT display, but can also be used for the VGA port on the Xilinx ML40x board. The design contains a PLB master interface that reads video data from a PLB attached memory device (not part of this design) and displays the data onto the TFT screen.
  • Page 72 Master bus request Mn_RNW Output Master read/not write Mn_size[0:3] Output Master transfer size Mn_type[0:2] Output Master transfer type Mn_wrBurst Output Master burst write transfer indicator Mn_wrDBus[0:63] Output Master write data bus www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 73 TFT_LCD_DE Output Data Enable TFT_LCD_CLK Output Video Clock TFT_LCD_DPS Output Selection of Scan Direction TFT_LCD_R[5:0] Output Red Pixel Data TFT_LCD_G[5:0] Output Green Pixel Data TFT_LCD_B[5:0] Output Blue Pixel Data ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...
  • Page 74 This causes a black screen to be displayed on reset. 1 = Enable TFT display on reset. This causes the PLB TFT LCD controller to operate normally on reset. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 75: Hardware

    TFT clock frequency can be reduced. However, reducing the TFT clock frequency also lowers the refresh rate of the screen. This leads to a noticeable flicker on the screen if the TFT clock is too slow. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 76: Video Timing

    D (1,Y) D (639,Y) Invalid thp = 96 TFT Clocks thb = 48 TFT Clocks DE = 640 TFT Clocks thf = 16 TFT Clocks UG082_08_03_050406 Figure 8-3: Horizontal Data www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...
  • Page 77 D(639,Y) Invalid tvp = 2 h_syncs tvb = 31 h_syncs DE = 640 TFT Clocks tvf = 12 h_syncs Display period is 480 h_syncs UG082_08_05_050406 Figure 8-5: Vertical Data ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

  • Page 78: Memory Map

    000000 = darkest → 111111 = brightest [17:16] Undefined. [15:10] Green Pixel Data: 000000 = darkest→111111 = brightest [9:8] Undefined. [7:2] Blue Pixel Data: 000000 = darkest→111111 = brightest [1:0] Undefined. www.xilinx.com ML40x EDK Processor Reference Design UG082 (v5.0) June 30, 2006...

  • Page 79: Control Registers (Dcr Interface)

    PLB read transactions. 1 = Enable TFT display. This causes the PLB TFT LCD controller to operate normally. ML40x EDK Processor Reference Design www.xilinx.com UG082 (v5.0) June 30, 2006...

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