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R
GPIO LED Interface
All LEDs connected to the GPIO lines illuminate Green when driven with a logic zero and
extinguish with a logic one.
FPGA to the non-inverting buffer (U36).
Table 2-6: GPIO LED Connection from FPGA to U36
UCF Signal Name
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7
GPIO LCD Interface
The GPIO signals used to connect to the 16 pin LCD header (J13) are organized into two
types of I/O, output only and input/output. There are three output only signals and eight
input/output signals. The eight input/outputs are controlled by the logic level of the
FPGA_LCD_DIR signal. Driving FPGA_LCD_DIR to a logic one configures the LVCC3245
to drive the J13 connector while a logic zero configures the LVCC3245 to drive the
XC2VP30.
Table 2-7
Table 2-7: GPIO LCD Data Bus Connection from FPGA to U35
UCF Signal Name
FPGA_LCD_DB0
FPGA_LCD_DB1
FPGA_LCD_DB2
FPGA_LCD_DB3
FPGA_LCD_DB4
FPGA_LCD_DB5
FPGA_LCD_DB6
FPGA_LCD_DB7
FPGA_LCD_DIR
32
Chapter 2: ML310 Embedded Development Platform
Table 2-6
XC2VP30 Pin
(U37)
H13
G13
C10
C11
J14
H14
E14
D14
shows the data bus signals on the GPIO LCD interface from the FPGA to U35.
XC2VP30 Pin
(U37)
F19
F20
F17
G17
B21
A21
G18
H18
C20
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shows the connections for the GPIO LEDs from the
Schem Signal
Name
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7
Schem Signal
Name
FPGA_LCD_DB0
FPGA_LCD_DB1
FPGA_LCD_DB2
FPGA_LCD_DB3
FPGA_LCD_DB4
FPGA_LCD_DB5
FPGA_LCD_DB6
FPGA_LCD_DB7
FPGA_LCD_DIR
UG068 (v1.01) August 25, 2004
LVC244 Buffer
LED
(U36)
2
DBG0
4
DBG1
6
DBG2
8
DBG3
11
DBG4
13
DBG5
15
DBG6
17
DBG7
LVCC3245
LCD I/F
Translator
(J13)
(U35)
3
7
4
8
5
9
6
10
7
11
8
12
9
13
10
14
2
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ML310 User Guide
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