Ddr Signaling; Ddr Memory Expansion - Xilinx ML310 User Manual

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DDR Signaling

The FPGA DDR DIMM interface supports SSTL2 signaling. All DDR signals are controlled
impedance and are SSTL2 terminated.

DDR Memory Expansion

The FPGA is capable of replicating up to three differential clock output pairs to the DIMM
in order to support either registered or unbuffered DIMMs. The ML310 DDR interface is
very flexible in the event different DDR memory is desired such as an unbuffered DIMM or
increased memory size. The DDR interface core delivered with EDK supports both
registered and unbuffered DRR Memory interfaces. Please review the EDK Processor IP
Reference Guide when migrating to a different DDR DIMM.
Table 2-1
the DDR_DQ signal names do not correlate as the FPGA uses IBM notation, Big Endian,
while the DDR DIMMs use Intel notation, Little Endian.
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
ddr_ad[0]
ddr_ad[1]
22
(U37)
BUFG
CLKIN
PLB_CLK
CLK0
CLKFB
CLK90_IN
CLK90
BUFG
DCM
CLKIN
CLK0
CLKFB
CLK90
Phase Shift
DCM
IBUFG
LVCMOS
25
DDR_CLK_FB_in
Figure 2-4: DDR DIMM Interface Block Diagram
lists the connections from the FPGA to the DDR DIMM interface. Please note that
XC2VP30 Pin
(U37)
AE23
AJ23
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Chapter 2: ML310 Embedded Development Platform
FDDRSE
DDR_CLK
D0
D1
C0
SSTL2_I
C1
FDDRSE
DDR_CLK_N
D0
D1
C0
SSTL2_I
C1
FDDRSE
D0 DDR_CLK_FB_out
D1
C0
LVCMOS
C1
25
BUFG
SSTL2_I
DDR_CLK90_in
C
CE
Q
BUFG
DQS_i
D
SSTL2_II
Schem Signal Name
DDR_A0
DDR_A1
DDR DIMM (P7)
ADDR
DDR Control
DDR_DQ/DQS
DIMM
(P7)
48
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ML310 User Guide
UG068 (v1.01) August 25, 2004