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Board Hardware
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
ddr_dq[32]
ddr_dq[33]
ddr_dq[34]
ddr_dq[35]
ddr_dq[36]
ddr_dq[37]
ddr_dq[38]
ddr_dq[39]
ddr_dq[40]
ddr_dq[41]
ddr_dq[42]
ddr_dq[43]
ddr_dq[44]
ddr_dq[45]
ddr_dq[46]
ddr_dq[47]
ddr_dq[48]
ddr_dq[49]
ddr_dq[50]
ddr_dq[51]
ddr_dq[52]
ddr_dq[53]
ddr_dq[54]
ddr_dq[55]
ddr_dq[56]
ddr_dq[57]
ddr_dq[58]
ddr_dq[59]
ddr_dq[60]
ddr_dq[61]
ddr_dq[62]
ddr_dq[63]
The connections from the FPGA to the DDR DIMM support either a registered or an
unbuffered DIMM. The only difference from a connectivity perspective is that the
ML310 User Guide
UG068 (v1.01) August 25, 2004
XC2VP30 Pin
(U37)
N27
P26
R25
R27
N28
P27
R26
R28
K27
L26
M27
N26
K28
L27
M28
N25
K25
K26
J27
J28
M25
M26
J25
J26
H28
G27
F28
E27
H27
G28
F27
E28
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Schem Signal Name
DDR_DQ31
DDR_DQ30
DDR_DQ29
DDR_DQ28
DDR_DQ27
DDR_DQ26
DDR_DQ25
DDR_DQ24
DDR_DQ23
DDR_DQ22
DDR_DQ21
DDR_DQ20
DDR_DQ19
DDR_DQ18
DDR_DQ17
DDR_DQ16
DDR_DQ15
DDR_DQ14
DDR_DQ13
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ09
DDR_DQ08
DDR_DQ07
DDR_DQ06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ01
DDR_DQ00
R
DIMM
(P7)
133
131
127
126
40
39
35
33
123
121
117
114
31
28
24
23
110
109
106
105
20
19
13
12
99
98
95
94
8
6
4
2
25
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