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Comparator Delay Test
Comparators V Offset Test
Comparator Run Test
Comparator Calibrations Test
16962A Logic Analyzer Service Guide
This test uses the pod, bonus, and calibration DACs, the
calibration oscillator (implemented in the interface FPGA),
the comparators, the connections between the comparators
and the Analysis chip, and the activity indicators in the
Analysis chip. We verify that we can use the DACs to control
the data input to the comparators. We verify that each
comparator data channel produces output. We verify that
each comparator output is connected to each ASIC data
input.
The comparator delay test verifies the integrity of all the
delay line elements for each delay line in the comparators.
Each delay line consists of 11 delay elements. When set for
maximum delay, all 11 elements are connected in series. If
any element is faulty, then data will not propagate through
the comparator. If this is the only test failing, then it is
almost certainly a bad comparator.
This test will not be executed if any probes are attached to
any of the probe cables. This test verifies that the V Offset
(offset null) taps for each data channel of each comparator
can be independently programmed and that each tap has the
expected effect on the V Offset adjustment. The tap settings
are programmable inside each comparator chip. If this is the
only test failing, then it is almost certain that is a bad
comparator.
The purpose of the Comparator Run Test is to verify some
specific paths through the comparator used during the start
of a run are working correctly.
The purpose of this test is to verify that each of the
comparator one- time calibrations can successfully be
performed. This verifies that all of the calibration circuitry
and components are within the tolerance limits required for
proper calibration. This test is executed only if all probes
are detached.
5
Troubleshooting
69
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