Acquisition Memory; Resource Bus Connectors; Mainframe Interface And Control Fpga - Agilent Technologies 16962A Service Manual

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Theory of Operation

Acquisition Memory

Resource Bus Connectors

Mainframe Interface and Control FPGA

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recognition, and counting functions. State or Timing sample
clocks are sent between cards in a multi- card module.
Sampled data is decelerated and passed to a Memory
Controller for storage in the Acquisition Memory RAM array.
The Acquisition IC also contains memory.
The Memory Controller stores data from the Acquisition ICs
into the Acquisition Memory. It also unloads data from the
memory array after an acquisition is complete, and it
delivers the data to the mainframe display system through
the mainframe interface connector. In addition, it can
perform a search of stored data.
The Acquisition Memory array is composed of DDR2
SDRAMs.
Connectors J10, J11, J12, and J13 route state clocks,
calibration signals, data search signals, control signals,
pattern recognition signals, and control clocks between all
cards in a multi- card module.
The Mainframe interface consists of an FPGA and the
Mainframe Interface Connector. The connector brings power
onto the card and provides for control of the card by the
analyzer mainframe. It also provides a path for unloading
acquired data to the analyzer display.
The FPGA converts bus signals generated by the mainframe
processor into control signals for the logic analyzer card. It
also provides centralized functions for the card such as I2C,
Calibration signals, Flag routing, and Timing mode sample
clock.
16962A Logic Analyzer Service Guide