Furuno FAR-2107 Series Service Manual page 437

7.3.3 SPU board (03P9337)
This board can be used commonly for FAR-2xx7 series.
1. Block diagram
The SPU board performs picture, LAN, video amplifier, ARPA and video plotter
processing in addition to the control over the whole radar. The CPU is comprised of
three components of Main CPU, ARPA CPU, DRW CPU.
IF-VIDEO-MIX
30M
U87
HPF
30M
LPF
FULL-LOG
OP1-VIDEO OUT
U78
SEMI-LOG
JP4
OP2-VIDEO OUT
U78
JP3
TP58
OP-VIDEO IN
U85
R401
+5V/+3.3V/+12V/-12V
TX ON
(From MAIN CPU)
MON MOTOR
(From PWRpcb))
U86:Video DET
U85
SEMI-LOG
FULL-LOG
JP6
TEST Echo
JP5
OP HD/BP/TRIG
OP-1 HD/BP/TRIG
OP-2 HD/BP/TRIG
RF Tx/Rx
GYRO CLK/Data
AIS TD
RS232C Tx/Rx RS232C TTL Tx/Rx
Fig. 7.3.5 Block diagram of the SPU board
U38
A/D
MONOTOR
Echo Data
U76
A/D
U46
8bit
SPU
FPGA
U64
CR8
FROM
U74
ARPA CPU
U56
SDRAM
LOG RD
GYRO RD
AIS RD
NAV RD
RSV1 TD
RSV2 TD
ARPA TD
KEY TD/RD
TRK TD/RD
7-32
7.3 Processor Unit (RPU-013)
U3
Display
MEMORY
U12
Echo
FPGA
U15
FROM
DATA/ADD
etc.
U27
SPU
Controller
U28
SDRAM
S1
U9
SDRAM
U22
SDRAM
U48
Flash ROM
(Program)
U13
U47
DRW FPGA
DATA ROM
(Backup)
CR4
U21
MAIN CPU
GC LED/UP/DOWN/HOLD
ANT ON
EXT ALM ACK
EXT ALM 1-4
U2
Echo
MEMORY
U1
Trail
MEMORY
LAN
To NET-100
CR6
U19
DRW CPU
To Display
U4
DVI
U5
DVI
U6
FROM