Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located on a
control panel at the front of the chassis. These connectors are designed specifically for use
with Supermicro chassis. See the figure below for the descriptions of the front control panel
buttons and LED indicators.
JSXB1A
C
A
LEDM1
JVRM1
JPG1
JPL2
JPL3
JPL2:
LAN 2/3/4/5
1-2:ENABLE
2-3:DISABLE
JPL3:
LAN 6/7/8/9
1-2:ENABLE
2-3:DISABLE
JPCIE3
JSXB1C
JL1:
CHASSIS
INTRUSION
USB 0/1
MH7
JUSB1
USB 2/3
S-SATA3
JPH1
S-SATA2
3
4
1
2
JPW1
7
LED2
UID
JUIDB1
MH6
A
LED3
LAN 2/3/4/5/6/7/8/9
JSDP3
JBM1
J1
JVGA1
COM2
JMD1_SRW1
JMD1_SRW2
JI2C1/JI2C2:
1-2:ENABLE
2-3:DISABLE
JWD1:WATCH DOG
1-2:RST
2-3:NMI
JMD2_SRW1
JPME2:
1-2:NORMAL
2-3:ME MANUFACTURING MODE
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
JSIM1
X11SDW-4C-TP13F+
REV:1.00
DESIGNED IN USA
JMD2:M.2-H
PCI-E 3.0 X2 / S-SATA4
MH2
JNVI2C1
JF1
JF1:
PWR
OH
HDD
PWR
NIC2
NIC1
RST X
ON
FF
LED
LED
JD1:
JPT1:TPM
1-2:ENABLE
1-3:PWR LED
4-7:SPEAKER
2-3:DISABLE
MH4
JBT1
LED1
Power LED
1
PWR
Power Button
Reset
Reset Button
3.3V
UID
3.3V Stby
3.3V Stby
3.3V Stby
3.3V
15
Figure 4-3. JF1 Header Definitions
63
Chapter 4: Motherboard Connections
PCB EDGE
PRESS FIT
PRESS FIT
COM1
USB 4/5(3.0)
LAN 1
IPMI_LAN
MH3
LEDT5
LEDT4
LEDT1
LEDT8
A
A
A
A
C
C
C
C
JLANLED2
A
A
A
A
C
JLANLED1
C
C
C
JTGLED2
LAN 12/13
LAN 10/11
J2
JMD3:M.2-P
PCI-E 3.0 X1
JTGLED1
JLANLED3
JPUSB1:
USB4/5 WAKE UP
1-2:ENABLE
2-3:DISABLE
JPL1:
LAN1
1-2:ENABLE
2-3:DISABLE
JMD3_SRW1
JMD1:M.2-H
JL1
PCI-E 3.0 X4 / I-SATA4
JSD1
BAR CODE
MH5
CPU
BT1
MH1
FAN4
FAN3
2
Ground
Ground
Power Fail LED
OH/Fan Fail
NIC2 Activity LED
NIC1 Activity LED
HDD LED
PWR LED
16
1
JPL1
JPI2C1
JGP1
S-SATA1
JSTBY1
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