Table of Contents
Advertisement
R-IN32M4-CL3 User's Manual: Board design edition
9. External MCU/Memory Interface Pins
9.2.2
Synchronous Burst Access MEMC
The synchronous burst access MEMC is externally connectable to paged ROM, ROM, SRAM, PSRAM, NOR-flash
memory, or peripheral devices with an interface similar to the SRAM interface via a 16- or 32-bit bus.
In addition, setting the ADMUXMODE pin to the high level enables multiplexing of the address and data signals.
The external MCU interfaces for the synchronous method burst access MEMC and the asynchronous SRAM MEMC are
multiplexed with each other. When the MEMCSEL and MEMIFSEL pins are set to high level and low level respectively,
the synchronous burst access MEMC can be used.
When both the BOOT0 and BOOT1 pins are at the low level, booting up proceeds from the memory connected to CSZ0.
R18UZ0074EJ0100
Page 42 of 61
Dec 24, 2019
Advertisement
Table of Contents
