Table of Contents
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7.
2.5-V built-in Regulator Peripheral Circuit Configuration ............................................................................ 21
7.1
Peripheral Connection Configuration with 2.5-V built-in Regulator ................................................................ 21
7.2
Peripheral Connection Configuration without 2.5-V built-in Regulator ........................................................... 21
7.3
Recommended Components of Inductor and Capacitors .................................................................................. 22
7.4
Recommended Component of Schottky barrier diode ...................................................................................... 22
7.5
Example of PCB Layout Image (23 mm Square BGA Package) ...................................................................... 23
7.5.1
L1 and L2 (23 mm Square BGA Package) .............................................................................................. 23
7.5.2
L3 and L4 (23 mm Square BGA Package) .............................................................................................. 23
7.6
Example of PCB Layout Image (17 mm Square BGA Package) ...................................................................... 24
7.6.1
L1 and L2 (17 mm Square BGA Package) .............................................................................................. 24
7.6.2
L3 and L4 (17 mm Square BGA Package) .............................................................................................. 24
7.7
Requirements for Parasitic Resistances and Parasitic Inductances in PCB ...................................................... 25
8.
Thermal Design ........................................................................................................................................... 26
8.1
Deciding on whether Particular Measures for Heat Dissipation are Required .................................................. 26
8.1.1
Estimating Tj ........................................................................................................................................... 26
8.1.2
Estimating Power Consumption .............................................................................................................. 26
Thermal Resistances under the JEDEC Conditions (for θja and Ψjt) ...................................................... 26
8.1.3
8.2
Examples of Measures for Heat Dissipation ..................................................................................................... 27
8.2.1
Measures for Heat Release in Designing the Board ................................................................................. 28
8.2.2
Heat Dissipation from the Periphery (Including the Casing) ................................................................... 30
8.3
Caution .............................................................................................................................................................. 31
8.3.1
Handling of Unused Pins ......................................................................................................................... 31
9.
External MCU/Memory Interface Pins ......................................................................................................... 32
9.1
External MCU Interface .................................................................................................................................... 33
9.1.1
Asynchronous-SRAM Supporting MCU Connection Mode ................................................................... 34
9.1.2
Synchronous-SRAM Supporting MCU Connection Mode ...................................................................... 35
9.1.3
Synchronous-Burst-Transfer Supporting MCU Connection Mode.......................................................... 36
9.2
External Memory Interface ............................................................................................................................... 39
9.2.1
Asynchronous SRAM MEMC ................................................................................................................. 39
9.2.2
Synchronous Burst Access MEMC ......................................................................................................... 42
Contents-2
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