Example Of Pcb Layout Image (23 Mm Square Bga Package); L1 And L2 (23 Mm Square Bga Package); L3 And L4 (23 Mm Square Bga Package); Figure 7.3 Example Of Pcb Layout Image (L1 And L2) (23 Mm Square Bga Package) - Renesas R-IN32M4-CL3 User Manual

R-IN32M4-CL3 User's Manual: Board design edition
7.5

Example of PCB Layout Image (23 mm Square BGA Package)

This section describes the peripheral circuit configuration of the 2.5-V built-in regulator installed in the R-IN32M4-CL3
in a 23 mm square BGA package.
7.5.1

L1 and L2 (23 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L1 and L2).
 Separate AGND of the built-in regulator from Digital GND as far as possible.
 Do not pass through AGND under the MDI signal and the inductor component (L).

Figure 7.3 Example of PCB Layout Image (L1 and L2) (23 mm Square BGA Package)

7.5.2

L3 and L4 (23 mm Square BGA Package)

Followings are layout conditions and an example of PCB layout image (at the lower left of the L3 and L4).
 Place C
as close to the power supply pins (VDDREG_33 and AVDDREG_33).
BYPASS
Also, place L, C , and C
IN
priority.
 Minimize the parasitic inductance of AVDDREG_33 pattern as small as possible.
The AVDDREG_33, AGND, and REG_OUT signals should be careful to avoid affecting other signals.
L3 at this position, where L2 is AGND,
is preferably AGND than other power
sources.
Place SBD, L, and C compactly in front
OUT
of this to connect to the PCB.
Don't make an unnecessarily wide pattern
to avoid functioning as an antenna.
SBD: Schottky Barrier Diode

Figure 7.4 Example of PCB Layout Image (L3 and L4) (23 mm Square BGA Package)

R18UZ0074EJ0100
Dec 24, 2019
PCB L1
VDD VDD
33 33
VDD
33
VDD
11
AVDD
REG_ VDD
REG_
EN 11
33
VDD
GND/
AGND REG_
OPEN
33
REG_
GND/ REG
AGND
OUT OPEN _FB
VDD
11A
P0_ P0_ P0_ P0_
GND
D3N D2N D1N D0N
P0_ P0_ P0_ P0_
GND GND GND GND GND GND GND
D3P D2P D1P D0P
Connect to GND at a single-point ground in front of this.
(In this case, do not use a ferrite bead.)
as close to the relevant pins as possible. In particular, placement of C
OUT
Removing the pattern
PCB L3 (VDD)
VDD
33
VDD
33
VDD
11
AVDD
VDD
REG_
REG_
EN 11
33
VDD
GND/
AGND REG_
OPEN
33
AGN REG_
REG_
GND/
D OUT OPEN FB
REG_OUT
P0_ P0_ P0_
D3N D2N D1N
P0_ P0_ P0_
D3P D2P D1P
SBD
L C
OUT
Place C
Also, place C
than that of SBD, inductor, and C
Do not place C
7. 2.5-V built-in Regulator Peripheral Circuit Configuration
Removing the pattern
PCB L2 (GND)
VDD
33
AVDD
REG_
REG_
EN
33
VDD
GND/
AGND REG_
OPEN
33
REG_ GND/
OUT OPEN
VDD
11A
AGND
P0_
D3N
P0_
D3P
Connect to AGND of C and C .
Do not pass AGND under the
IN OUT
MDI signal and the inductor
component (L).
Bypass capacitor for
VDDREG_33
Connect to GND
PCB L4
VDD VDD
33 33
REG_
EN
C
BYPASS
GND/
AGND
OPEN
REG_
AGND
OUT
VDD VDD
AVDDREG_33
11A 11A
P0_
D0N
P0_
C
IN
D0P
Minimize parasitic inductance
to AVDDREG_33.
as close to the power supply pin (VDDREG_33 and AVDDREG_33).
BYPASS
as close to the relevant pin as possible. (Placement of C
IN
.)
OUT
and C side by side to prevent noise propagation.
IN OUT
VDD VDD VDD
33 33 33
VDD
33
VDD
11
VDD
11
REG_
FB
VDD VDD
11A 11A
P0_ P0_ P0_
D2N D1N D0N
P0_ P0_ P0_
D2P D1P D0P
is a high
IN
Bypass capacitor for
AVDDREG_33
Connect to AGND
VDD VDD VDD
33 33 33
VDD
33
VDD
11
C
BYPASS
AVDD
VDD
REG_3
11
3
VDD
REG_3
3
REG_ REG_
GND/
OPEN FB FB
VDD VDD
11A 11A
P0_ P0_ P0_ P0_
D3N D2N D1N D0N
P0_ P0_ P0_ P0_
D3P D2P D1P D0P
This pattern is a 2.5-V feedback voltage after smoothing with the
inductor (L) and capacitor (C ).
OUT
Keep away from the regulator related signals and the inductor (L).
is high priority
IN
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