Operation Timing Of Memory Expansion Mode And Microprocessor Mode (Vcc1=3V) - Renesas M16C/6N User Manual

M306NKT-EPB User's Manual
4.2.2 Operation Timing of Memory Expansion Mode and Microprocessor Mode (Vcc=3V)
(1) Separate Bus Timing
Table 4.5 and Figure 4.4 show the bus timing in memory expansion mode and microprocessor mode (3 wait, accessing external
area).
Table 4.5 Memory expansion mode and microprocessor mode (3 wait, accessing external area)
Symbol
Address output delay time
td(BCLK-AD)
Address output hold time (BCLK standard)
th(BCLK-AD)
Address output hold time (RD standard)
th(RD-AD)
Address output hold time (WR standard)
th(WR-AD)
Chip-select output delay time
td(BCLK-CS)
th(BCLK-CS) Chip-select output hold time (BCLK standard)
td(BCLK-ALE) ALE signal output delay time
ALE signal output hold time
th(BCLK-ALE)
RD signal output delay time
td(BCLK-RD)
RD signal output hold time
th(BCLK-RD)
WR signal output delay time
td(BCLK-WR)
WR signal output hold time
th(BCLK-WR)
Data output delay time (BCLK standard)
td(BCLK-DB)
Data output hold time (BCLK standard)
th(BCLK-DB)
Data output delay time (WR standard)
td(DB-WR)
Data output hold time (WR standard)
th(WR-DB)
*1 Calculated by the following formula according to the frequency of BCLK.
( )
− ×
9
0 5 . 10
n
−
40
[ns] n: "3" for 3 wait
( )
f BCLK
*2 Calculated by the following formula according to the frequency of BCLK.
× 9
0 5 . 10
−
10
[ns]
( )
f BCLK
REJ10J0519-0200 Rev.2.00 Oct. 16, 2006
Item
4. Hardware Specifications
Actual MCU This product
[ns]
Min. Max. Min.
30
4 See left
0 -3
(*2) See left
30
4 See left
30
-4 See left
30
0 See left
30
0 See left
40
4 See left
(*1) See left
(*2) See left
[ns]
Max.
See left
See left
See left
See left
See left
See left
Page 77 of 104