Renesas M16C/6N User Manual page 81

M306NKT-EPB User's Manual
(2) Multiplex Bus Timing
Table 4.6 and Figure 4.5 show the bus timing in memory expansion mode and microprocessor mode (2 wait, accessing external
area and using multiplex bus).
Table 4.6 Memory expansion mode and microprocessor mode (2 wait, accessing external area and using multiplex bus)
Symbol
td(BCLK-AD) Address output delay time
Address output hold time (BCLK standard)
th(BCLK-AD)
Address output hold time (RD standard)
th(RD-AD)
Address output hold time (WR standard)
th(WR-AD)
Chip-select output delay time
td(BCLK-CS)
Chip-select output hold time (BCLK standard)
th(BCLK-CS)
Chip-select output hold time (RD standard)
th(RD-CS)
Chip-select output hold time (WR standard)
th(WR-CS)
RD signal output delay time
td(BCLK-RD)
RD signal output hold time
th(BCLK-RD)
WR signal output delay time
td(BCLK-WR)
WR signal output hold time
th(BCLK-WR)
td(BCLK-DB) Data output delay time (BCLK standard)
th(BCLK-DB) Data output hold time (BCLK standard)
Data output delay time (WR standard)
td(DB-WR)
Data output hold time (WR standard)
th(WR-DB)
ALE output delay time (BCLK standard)
td(BCLK-ALE)
ALE output hold time (BCLK standard)
th(BCLK-ALE)
ALE output delay time (Address standard)
td(AD-ALE)
ALE output hold time (Address standard)
th(ALE-AD)
After address RD signal output delay time
td(AD-RD)
After address WR signal output delay time
td(AD-WR)
Address output floating start time
tdz(RD-AD)
*1 Calculated by the following formula according to the frequency of BCLK.
×
9
0 5 . 10
−
10
[ns]
( )
f BCLK
*2 Calculated by the following formula according to the frequency of BCLK.
( )
− × 9
0 5 . 10
n
−
50
[ns] n: "2" for 2 wait
( )
f BCLK
*3 Calculated by the following formula according to the frequency of BCLK.
×
9
0 5 . 10
−
40
[ns]
( )
f BCLK
*4 Calculated by the following formula according to the frequency of BCLK.
× 9
0 5 . 10
−
15
[ns]
( )
f BCLK
REJ10J0519-0200 Rev.2.00 Oct. 16, 2006
Item
4. Hardware Specifications
Actual MCU This product
[ns]
Min. Max. Min.
50
4 See left
(*1) See left
(*1) See left
50
4 See left
(*1) See left
(*1) See left
40
0 See left
40
0 See left
50
4 See left
(*2) See left
(*1) See left
40
-4 See left
(*3) See left
(*4) See left
0 See left
0 See left
8
[ns]
Max.
See left
See left
See left
See left
See left
See left
15
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