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M306NKT-EPB User's Manual
(3) Timing Requirements
Table 4.7 and Figure 4.6 show timing requirements in memory expansion mode and microprocessor mode.
Table 4.7 Timing requirements
Symbol
Data input setup time
tsu(DB-RD)
RDY# input setup time
tsu(RDY-BCLK)
HOLD# input setup time
tsu(HOLD-BCLK)
Data input hold time
th(RD-DB)
RDY# input hold time
th(BCLK-RDY)
HOLD# input hold time
th(BCLK-HOLD)
td(BCLK-HLDA)
HLDA# output delay time
Common to "with wait" and "no wait" (actual MCU)
BCLK
tsu(HOLD-BCLK)
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
- P5
0
2
Common to "with wait" and "no wait" (this product)
BCLK
tsu(HOLD-BCLK)
HOLD input
HLDA output
P0,P1,P2,P3,P4,
P5
- P5
0
2
Figure 4.6 Timing requirements
* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
REJ10J0519-0200 Rev.2.00 Oct. 16, 2006
Item
th(BCLK-HOLD)
td(BCLK-HLDA)
H i -Z
th(BCLK-HOLD)
td(BCLK-HLDA)
Hi-Z
Actual MCU
[ns]
Min.
Max.
50
40
50
0
0
0
40
td(BCLK-HLDA)
td(BCLK-HLDA)
4. Hardware Specifications
This product
[ns]
Min.
Max.
65
55
65
See left
See left
See left
See left
Page 81 of 104
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