Ricoh PRIPORT VT 2000 Series Service Manual page 47

28 February '91
2.5.2 Peak Hold:
CCD Board
OS
CCD
Image
Processing
Board
(CN403-27)
CN403-25
Read
(CN403-29)
CN403-27
Write
(CN403-31)
CN403-29
S LSYNC
(CN403-33)
CN403-31
S CLK
This circuit holds, at different stages of image processing, the peak white
levels for both the original and the platen cover (standard white). The peak
white, or maximum, level is stored as charge on a capacitor. The peak hold
circuit is cleared by discharging the capacitor.
1). Platen Cover Peak Hold (Standard White)
The platen cover peak hold is used as standard white when processing
data to create the shading distortion data, which is later stored in memory.
This data is used to correct such distortions as bright or dull spots on the
lamp or variations in the CCD output. To create the platen cover peak hold
(standard white), the peak hold circuit stores the maximum level from five
scan lines of the platen cover.
2). Original Background Peak Hold
The maximum white level of the original, stored in the peak hold circuit, is
used to shift the threshold voltage of the D/A converter to match the original
background. An area of the original, 64 mm wide (from S2,048 to S3,072),
is read. This corresponds to a small size original.
3). Peak Hold Set Signal
The peak hold set signal (PKHST) clears the peak hold circuit. The peak
hold timing signal (PKHTM) turns on the analog switch (SW2) allowing the
image signal to be applied to the peak hold circuit.
Inverter Amp
Timing
Signal
Generator
( ): VT2300/VT2500
2-20
A/D Conversion Board
Vo
PKHTM
PKHST Peak Hold
Circuit
BLSET
SHMRT A/D Conversion
A/D Conversion
SW2
VPH