ADLINK Technology cExpress-KL User Manual page 68

7.3.7.1. PCI and PCIe > PCI Express Configuration
Feature
PCI Express Configuration
PCI Express Clock Gating
DMI Link ASPM Control
Port8xh Decode
Compliance Test Mode
PCI Express Gen3 EQ Lanes
PCI Express Root Port X
PCI and PCIe > PCI Express Configuration > PCI Express Gen3 EQ Lanes
Feature
Override SW EQ settings
PCI and PCIe > PCI Express Configuration > PCI Express Root Port X
Feature
PCI Express Root Port
Topology
ASPM Support
L1 Substates
Gen3 Eq Phase3 Method
UPTP
DPTP
ACS
62
Options Description
Info only
Disabled Enable/Disable PCI Express Clock Gating for each
root port.
Enable
The control of Active State Power Management of
Disabled
the DMI Link.Auto is equal to POR setting.
Enable
Disabled PCI Express Port8xh Decode Enable/Disable.
Disabled Enable when using Compliance Load Board.
Submenu
Submenu
Options
Disabled
Enable
Options
Disabled
Enable
Unknown
x1
x4
Sata Express
M2
Auto
L0s
L1
L0sL1
Disabled
Disabled
L1.1
L1.2
L1.1 & L1.2
Hardware
Static Coeff
Software Search
5
7
Disable
Enable
Description
Override SW EQ settings
Description
Control the PCI Express Root Port.
Identify the SATA Topology: Default, ISATA,
Flex, DirectConnect or M2.
Set the ASPM Level.
Force L0s - Force all links to L0s State
Auto - BIOS auto configure;
Disabled - Disables ASPM
PCI Express L1 Substates settings.
PCIe Gen3 Equalization Phase 3 Method
Upstream Port Transmitter Preset.
Downstream Port Transmitter Preset
Enable/Disable Access Control Services
Extended Capability.
BIOS Setup