ADLINK Technology NuIPC cPCI-7300A User Manual
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ADLINK Technology NuIPC cPCI-7300A User Manual

80mb ultra-high speed 32-ch digital i/o boards
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  • Page 1 sales@artisantg.com artisantg.com (217) 352-9330 | Visit our website - Click HERE...
  • Page 2 ® ® NuIPC / NuDAQ cPCI-7300A & PCI-7300A 80MB Ultra-High Speed 32-CH Digital I/O Boards User’s Guide Recycle Paper...
  • Page 3 ©Copyright 2002 ADLINK Technology Inc. All Rights Reserved. Manual Rev 2.22: July 16, 2002 Part No.: 50-11106-100 The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.
  • Page 4 Getting service from ADLINK • Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us. ADLINK Technology Inc. Web Site http://www.adlinktech.com Sales & Service@adlinktech.com Service NuDAQ + USBDAQ nudaq@adlinktech.com...

  • Page 6: Table Of Contents

    Table of Contents Introduction................1 1.1 A ....................2 PPLICATIONS 1.2 F ..................... 2 EATURES 1.3 S ................... 3 PECIFICATIONS 1.4 S ................5 OFTWARE UPPORTING 1.4.1 Programming Library..............5 ® 1.4.2 PCIS-LVIEW: LabVIEW Driver..........5 1.4.3 PCIS-VEE: HP-VEE Driver............6 1.4.4 DAQBench : ActiveX Controls..........
  • Page 7 4.3 D I/O D ................28 IGITAL 4.4 I FIFO FIFO ..............29 NPUT UTPUT 4.5 B DMA ................30 MASTERING 4.6 S DMA................31 CATTER GATHER 4.7 C ..................32 LOCKING 4.8 S ..................33 TARTING 4.9 A ..................34 CTIVE ERMINATOR 4.10 D .............34 IGITAL NPUT PERATION 4.10.1...
  • Page 8 5.19 _7300_DO_DMA_S ..............63 TATUS 5.20 _7300_DO_DMA_A ...............63 BORT 5.21 _7300_DO_PG_S ................64 TART 5.22 _7300_DO_PG_S ................65 5.23 _7300_DI_T ..................65 IMER 5.24 _7300_DO_T ...................66 IMER 5.25 _7300_I ..................66 IMER 5.26 _7300_G ................67 AMPLE 5.27 _7300_S ................68 AMPLE 5.28 _7300_G ...............68 NDERRUN TATUS Appendix A 8254 Programmable Interval Timer....70 A.1 T (NEC) 8254 ................70...
  • Page 9 How to Use This Guide This manual is designed to help you use the cPCI-7300 and PCI-7300A Rev.B. The manual describes how to modify various settings on the PCI-7300A card to meet your requirements. It is divided into five chapters: •...

  • Page 10: Introduction

    Introduction The cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed digital I/O card, it consists of 32 digital input or output channel. High performance designs and the state-of-the-art technology make this card to be ideal for high speed digital input and output applications. The cPCI/PCI-7300A performs high-speed data transfers using bus mastering DMA and scatter/gather via 32-bit PCI bus architecture.

  • Page 11: Applications

    1.1 Applications • Interface to high-speed peripherals • High-speed data transfers from other computers • Automated test equipment (ATE) • Electronic and logic testing • Interface to external high-speed A/D and D/A converter • Digital pattern generator • Waveform and pulse generation •...

  • Page 12: Specifications

    1.3 Specifications ♦ Digital I/O (DIO) • Numbers of Channel: 32 TTL compatible inputs and/or outputs • Device: IDT 74FCT373 • I/O Configurations: 16 DI & 16 DO 32 DI 32 DO ♦ Input Voltage: • Low: Min. 0V; Max. 0.8V •...
  • Page 13 • Mode: Bus Mastering DMA with Scatter/Gather • Data Transfers: 8/16/32-bit input or output (programmable) ♦ DMA Transfer count: • 2M double words (8M bytes) for non-chaining mode DMA • No limitation for chaining mode (scatter/gather) DMA ♦ Max. Transfer rate: •...

  • Page 14: Software Supporting

    1.4 Software Supporting ADLINK provides versatile software drivers and packages for users’ different approach to built-up a system. We not only provide programming library such as DLL for many Windows systems, but also provide drivers for software ® packages such as LabVIEW , HP VEE , DASYLab , InTouch...

  • Page 15: Pcis-Vee: Hp-Vee Driver

    1.4.3 PCIS-VEE: HP-VEE Driver The PCIS-VEE includes the user objects, which are used to interface with HP VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE drivers are free shipped with the board. You can install and use them without license.

  • Page 16: Installation

    Installation This chapter describes how to install the cPCI/PCI-7300A. At first, the contents in the package and unpacking information that you should be careful are described. Because the PCI-7300A is following the PCI design philosophy, it is no more jumpers and DIP switches setting for configuration. The Interrupt and I/O port address are the variables associated with automatic configuration, the resource allocation is managed by the system BIOS.

  • Page 17: Unpacking

    2.2 Unpacking Your cPCI/PCI-7300A card contains sensitive electronic components that can be easily damaged by static electricity. The card should be placed on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

  • Page 18: Pci-7300A's Layout

    2.4 PCI-7300A's Layout Figure 2.1 PCI-7300A Layout Diagram Installation • 9...
  • Page 19 Figure 2.2 cPCI-7300A Layout Diagram 10 • Installation...

  • Page 20: Hardware Installation Outline

    2.5 Hardware Installation Outline PCI configuration The PCI cards (or CompactPCI cards) are equipped with plug and play PCI controller, it can request base addresses and interrupt according to PCI standard. The system BIOS will install the system resource based on the PCI cards’...

  • Page 21: Connector Pin Assignment

    2.6 Connector Pin Assignment The PCI-7300A comes equipped with one 100-pin SCSI type connector (CN1) located on the rear mounting plate. The pin assignment of CN1 is illustrated in the figure 2.2. Legend: Signal Pins Signal Name Signal Type Description Direction Ground –...
  • Page 22 PA10 PA11 PA12 PA13 PA14 PA15 DI_TRG DI_REQ DI_ACK AUXI0 AUXI1 AUXI2 AUXI3 TERMPWR TERMPWR TERMPWR TERMPWR AUXO0 AUXO1 AUXO2 AUXO3 DO_TRG DO_REQ DO_ACK PB10 PB11 PB12 PB13 PB14 PB15 Figure 2.2 CN1 Pin Assignment Installation • 13...

  • Page 23: Wiring And Termination

    2.7 Wiring and Termination Transmission line effects and environment noise, particularly on clock and control lines, can lead to incorrect data transfers if you do not take care when running signal wires to and from the devices. Take the following precautions to ensure a uniform transformation line and minimize noise pickup: 1.

  • Page 24: Daughter Board Supporting

    2.8 Daughter Board Supporting The cPCI/PCI-7300A can be connected with two daughter boards: DIN-100S or DIN-502S. The functionality and connections are specified as follows. 2.8.1 Connect with DIN-100S The DIN-100S is a direct connection for the add-on card that is equipped with SCSI-100 connector.

  • Page 25: Registers

    Registers In this chapter, the registers’ format of the cPCI/PCI-7300A is described. Please note that the registers’ map of the PCI-7300A Rev.B is different from the PCI-7300A Rev.A This information is quite useful for the programmers who wish to handle the card by low-level programming.

  • Page 26: I/O Port Base Address

    3.1 I/O Port Base Address The registers of the cPCI/PCI-7300A are shown in Table 3.1. The base address of these registers is als o assigned by the PCI P&P BIOS. The assigned base address is stored at offset 18h of the PCR. Therefore, users can read the PCR to know the base address by using BIOS function call.

  • Page 27: Di_Csr: Di Control & Status Register

    3.2 DI_CSR: DI Control & Status Register Digital input control and status checking is done by this register. Address: BASE + 00 Attribute: READ/WRITE Data Format: Bit # 3~0 DI_HND_SHK DI_CLK_SEL DI_32 PA_TERM_OF DI_WAIT_TRI Bit # 7~4 -- (1) Bit # 11~8 DI_FIFO_FULL DI_OVER DI_FIFO_CLR...

  • Page 28: Do_Csr: Do Control & Status Register

    DI_FIFO_CLR (R/W) 0: No effect 1: Clear digital input FIFO. If both PORTA and PORTB are configured as inputs, both FIFO will be cleared. Always get 0 when read. DI_OVER (R/W) 0: DI FIFO does not full during input sampling 1: DI FIFO full during input sampling, some input data was lost, write “1”...
  • Page 29 DO_WAIT_NAE (R/W) 0: do not wait output FIFO not almost empty flag 1: delay output data until FIFO is not almost empty PAT_GEN(R/W) 0: pattern generation disable (FIFO data do not repeat during data output) 1: pattern generation enable (FIFO data repeat themselves during data output) DO_WAIT_TRIG (R/W) 0: delay output data until DOTRIG is actived...

  • Page 30: Auxiliary Digital I/O Register

    BURST_HNDSHK (R/W) 0: disable burst handshaking mode 1: enable burst handshake mode * Note: This bit is for Rev.B only. 3.4 Auxiliary Digital I/O Register Auxiliary 4-bit digital inputs and 4 -bit digital outputs Address: BASE + 08 Attribute: READ/WRITE Data Format: Bit # 3~0 DO_AUX_3...

  • Page 31: Di_Fifo: Di Fifo Direct Access Port

    T2_EN (R/W) 0: Disable Timer2 interrupt 1: Interrupt CPU on falling edge of Timer 2 output AUXDI0_INT (R/W) 0: AUXDI does not generate interrupt 1: AUXDI interrupt occurred. Write “1” to clear T2_INT (R/W) 0: Timer 2 does not generate interrupt 1: Timer 2 interrupt occurred.

  • Page 32: Do_Fifo: Do External Data Fifo Direct Access Port

    3.7 DO_FIFO: DO external data FIFO direct access port The digital output FIFO data can be accessed through this port directly. Address: BASE + 0x0C Attribute: READ/WRITE Data Format: Bits Bit # 7~0 DO_FIFO_8 Bit # 15~8 DO_FIFO_16 Bit # 31_16 DO_FIFO_32 DO_FIFO_8 Bit 7 ~ Bit 0 of digital output FIFO...

  • Page 33: Fifo_Cr: Fifo Almost Empty/Full Register

    3.8 FIFO_CR: FIFO almost empty/full register The register is used to control the FIFO programmable almost empty/full flag. Address: BASE + 0x018 Attribute: WRITE Only Data Format: Bits Bit 15~0 PB_PAE_PAF Bit 31_16 PA_PAE_PAF PB_PAE_PAF (WO) Programmable almost empty/full threshold of PORTB FIFO, 2 consecutive writes are required to program PORTB FIFO.

  • Page 34: Plx Pci-9080 Dma Control Registers

    DI_ACK_NEQ (R/W) 0: DI_ACK is rising edge active 1: DI_ACK is falling edge active DI_TRG_NEQ (R/W) 0: DI_TRG is rising edge active 1: DI_TRG is falling edge active DO_REQ_NEQ (R/W) 0: DO_REQ is rising edge active 1: DO_REQ is falling edge active DO_ACK_NEQ (R/W) 0: DO_ACK is rising edge active 1: DO_ACK is falling edge active...

  • Page 35: Operation Theory

    Operation Theory This chapter provides detailed operation information cPCI/PCI-7300A, including I/O configuration, block diagram, input/output FIFO, bus -mastering DMA, scatter/gather, clocking mode, starting mode, termination, I/O transfer mode, and auxiliary digital I/O. 4.1 I/O Configuration The 32-bit I/O data path of PCI-7300A can be configured as 8-bit, 16-bit, or 32-bit, the possible configuration modes are listed as follows.

  • Page 36: Block Diagram

    Notes: PORTA is default as Input channel; PORTB is default as output channel. In DI32 mode, the PORTB has to be configured as the extension of PORTA, that is, PORTB is the input port (DI16…DI31). PORTB control signals are disabled. In DO32 mode, the PORTA has to be configured as the extension of PORTB, that is, PORTA is the output port (DO16…DO31).

  • Page 37: Digital I/O Data Flow

    AUX DI 3..0: Four auxiliary digital inputs DITRIG: Digital input trigger line DIACK/DIREQ: Digital input handshaking signals DOTRIG: Digital output trigger line DOACK/DOREQ:Digital output handshaking signals 4.3 Digital I/O Data Flow When applying digital input functions, the data will be sampled into the input FIFO periodically as we configured and then transfer to the system memory by the bus mastering DMA of the PCI Bridge.

  • Page 38: Input Fifo And Output Fifo

    4.4 Input FIFO and Output FIFO Due to the data transfer rate between external devices and the cPCI/PCI-7300A is independent from that between cPCI/PCI-7300A and PCI bus. Two 16K words FIFO are provided to be I/O buffers. For digital input operation, data is sampled and transferred to the input FIFO. When the input FIFO is non-empty, the PCI bridge will automatically transfer the data from the input FIFO to the system memory in the background when PCI bus is available.

  • Page 39: Bus-Mastering Dma

    4.5 Bus-mastering DMA Digital I/O data transfer between PCI-7300A and PC’s system memory is through bus mastering DMA, which is controlled by PCI bridge chip PLX PCI-9080. The PCI bus master means the device requires fast access to the bus or high data throughput in order to achieve good performance. However, users should note that when more than one bus masters request the bus ownership, all masters will share the bandwidth of PCI bus and the performance of each master will unavoidably drop.

  • Page 40: Scatter/Gather Dma

    4.6 Scatter/gather DMA The PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the users to transfer a large amount of data by linking the all memory blocks into a continuous linked list. In the multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on. It is difficult to allocate a large continuous memory block to do the DMA transfer.

  • Page 41: Clocking Mode

    In non-chaining mode, the maximum DMA data transfer size is 2M double words (8M bytes). However, by using chaining mode, scatter/gather, there is no limitation on DMA data transfer size. Users can also link the descriptor nodes circularly to achieve a double-buffered mode DMA. 4.7 Clocking Mode The data input to or output from the FIFO is operated in a specific rate.

  • Page 42: Starting Mode

    for the assertion of DI-ACK. If the external device follows the rule, there would be no data lost due to FIFO overrun. 3. Handshaking: For the digital input, through DI-REQ input signal from external device and DI-ACK output signal to the external deviec, the digital input can have simple handshaking data transfer.

  • Page 43: Active Terminator

    2. WaitTRIG: The data transfer will not start until external trigger signal (DI-TRIG for digital input, DO-TRIG for digital output) is activated. 3. WaitFIFO: This starting mode is only available for digital output. The data transfer is started until the output FIFO is not almost empty. The threshold of FIFO almost empty is software programmable.
  • Page 44 4. Define the starting mode to be NoWait or WaitTRIG. 5. The digital input data are stored in the input FIFO after a DI command is issued and waiting for DI-TRIG signal if in WaitTRIG mode. 6. The data in the input FIFO will be transferred into system memory directly and automatically by bus mastering DMA.

  • Page 45: Digital Input Dma In External Clock Mode

    Notes: When the DMA function of digital input starts, the input data will be stored in the FIFO of the cPCI/PCI-7300A. The data then transfer to system memory i f PCI bus is available. If the speed of translation from external device to the FIFO on board is higher than that from FIFO to system memory or the PCI bus is busy for a long time, the FIFO become full and overrun situation occurs after the next data being...
  • Page 46 The operation flow is show as below: The followings are timing diagrams of the DI-REQ and the input data. The active edge of DI-REQ can be programmed by the function 5.5. DIREQ as input data strobe (when Rising Edge Active) Operation Theory •...

  • Page 47: Digital Input Dma In Handshaking Mode

    DIREQ as input data strobe (when Falling Edge Active) Notes: From the timing diagram of external clock mode, the maximum frequency can be up to 40MHz. However, users should note that when the sampling frequency of digital input is higher than the PCI bus bandwidth (33Mhz), or the bandwidth of chipset (30Mhz typically) from PCI bus to system memory.
  • Page 48 8. The data saved in FIFO will transfer to system memory of your computer directly and automatically by bus mastering DMA. The operation flow is show as below: The following figure shows the timing requirement of the handshaking mode digital input operation. DIREQ &...

  • Page 49: Continuous Digital Input

    4.10.4 Continuous Digital Input If the digital input operation still active after the competition of the previous DMA transfer and do not clear the data in the input FIFO when the next DMA starts, the cPCI/PCI-7300A can achieve the continuous digital input function in a high-speed sampling rate.

  • Page 50: Digital Output Operation Mode

    Notes: The latency time between two DMA transfers is different from the PCI bus latency time mentioned in the previous section of “Bus Mastering”. The former means the time difference between two continuous DMA processes started by the software. And the latter means the time difference between two continuously hardware DMA requests on the PCI bus within a DMA process.

  • Page 51: Digital Output Dma In Handshaking Mode

    As the data output in the internal clock mode, the DOREQ signal could be use as the output strobe to indicate the output operation to the external device. The timing diagram of the DOREQ is shown as follows: DOREQ as output data strobe 4.11.2 Digital Output DMA in Handshaking Mode For digital output, through DO-REQ output signal and DO-ACK input signal, the digital output can have simple handshaking data transfer.
  • Page 52 The operation flow is show as below: The timing diagram of the DOREQ and DOACK in the DO handshaking mode is shown as follows: DOREQ & DOACK Handshaking Note: DOACK must be deserted before DOREQ asserts, DOACK can be asserted any time after DOREQ asserts, DOREQ will be reasserted after DOACK is asserted.

  • Page 53: Digital Output Dma In Burst Handshaking Mode

    4.11.3 Digital Output DMA in Burst Handshaking Mode The burst handshaking mode is a fast and reliable data transfer protocol. It has both advantage of handshaking mode, which is reliable, and the advantage of internal clock mode, which is fast. When using this mode, the sender has to check the availability of receiver indicated by the DO-ACK signal before it starts to send data.

  • Page 54: Pattern Generator

    The operation flow is show as below: Notes: When the DMA function of digital output starts, the output data will transfer to the output FIFO of cPCI/PCI-7300A when PCI bus is available. If the speed of translation from the FIFO on board to the external device is higher than that from system memory to the output FIFO or the PCI bus is busy for a long time, the FIFO become empty and under-run situation occurs after the next data being read from the...

  • Page 55: Auxiliary Dio

    4. Set the output patterns into the output FIFO by direct FIFO access 5. Start the pattern generator function. 6. The pattern generator function will not stop until users stop the process 4.12 Auxiliary DIO The cPCI/PCI-7300A also includes four auxiliary digital inputs and four digital outputs, which can be applied to achieve the simple I/O functions.

  • Page 56: C/C++ Libraries

    C/C++ Libraries This chapter describes the software library for operating this card. Only the functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included in ADLINK CD, for the descriptions of the Windows 98/NT/2000 DLL functions. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95).

  • Page 57: Programming Guide

    5.2 Programming Guide 5.2.1 Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software driver are using full-names to represent the functions' real meaning. The naming convention rules are: In DOS Environment : _{hardware_model}_{action_name}. e.g. _7300_Initial(). All functions in PCI-7300A driver are with 7300 as {hardware_model}.

  • Page 58: 7300_I Nitial

    5.3 _7300_Initial @ Description A PCI-7300A card is initialized according to the card number. Because the cPCI/PCI-7300A is PCI bus architecture and meets the plug and play design, the IRQ and base address (pass-through address) are assigned by system BIOS directly. Every cPCI/PCI-7300A card has to be initialized by this function before calling other functions.

  • Page 59: 7300_Close

    5.4 _7300_Close @ Description Close a previously initialized PCI-7300A card. @ Syntax Visual C/C++ (Windows 95) int W_7300_Close (int card_number) Visual Basic (Windows 95) W_7300_Close (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_Close (int card_number) @ Argument card_number: The card number of the PCI-7300A card.
  • Page 60 DI8DO16: PORTA is 8 -bit input and PORTB is 16-bit output DI16DO8: PORTA is 16-bit input and PORTB is 8 -bit output DI16DO16: PORTA is 16-bit input and PORTB is 16-bit output term_cntrl: the terminator control PAOFF_PBOFF: PORTA terminator OFF, PORTB terminator OFF PAOFF_PBON:...

  • Page 61: 7300_Di_Mode

    5.6 _7300_DI_Mode @ Description Set the clock mode and start mode for the PCI-7300A DI operation. @ Syntax Visual C/C++ (Windows 95) W_7300_DI_Mode (int card_number, clk_mode, start_mode) Visual Basic (Windows 95) W_7300_DI_Mode (ByVal card_number As Long, ByVal clk_mode As Long, ByVal start_mode As Long) As Long C/C++ (DOS) _7300_DI_Mode...

  • Page 62: 7300_Do_Mode

    5.7 _7300_DO_Mode @ Description Set the clock mode and start mode for the PCI-7300A DO operation. @ Syntax Visual C/C++ (Windows 95) W_7300_DO_Mode (int card_number, clk_mode, start_mode, int fifo_threshold) Visual Basic (Windows 95) W_7300_DO_Mode (ByVal card_number As Long, ByVal clk_mode As Long, ByVal start_mode As Long, ByVal fifo_threshold As Long) As Long C/C++ (DOS)

  • Page 63: 7300_Aux_Di

    5.8 _7300_AUX_DI @ Description Read data from auxiliary digital input port. You can get all 4 bits input data by using this function. @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DI (int card_number, int *aux_di) Visual Basic (Windows 95) W_7300_AUX_DI (ByVal card_number As Long, aux_di As Long) As Long C/C++ (DOS) int _7300_AUX_DI (int card_number, int *aux_di) @ Argument...

  • Page 64: 7300_Aux_Do

    card_number: The card number of the PCI-7300A card. di_ch_no: the DI channel number, the value has to be set within 0 and 3. aux_di: return value, either 0 or 1. @ Return Code NoError PCICardNumErr PCICardNotInit InvalidDIOChNum 5.10 _7300_AUX_DO @ Description Write data to auxiliary digital output port.

  • Page 65: 7300_A Lloc

    @ Syntax Visual C/C++ (Windows 95) int W_7300_AUX_DO_Channel (int card_number, int do_ch_no, int do_data) Visual Basic (Windows 95) W_7300_AUX_DO_Channel (ByVal card_number As Long, ByVal do_ch_no As Long, ByVal do_data As Long) As Long C/C++ (DOS) int _7300_AUX_DO_Channel (int card_number, int do_ch_no, int do_data) @ Argument card_number:...

  • Page 66: 7300_F Ree

    @ Return Code NoError AllocDMAMemFailed 5.13 _7300_Free_DMA_Mem @ Description Deallocate a system DMA memory under Windows 95 environment. This function is only available in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Free_DMA_Mem (HANDLE memID) Visual Basic (Windows 95) W_7300_Free_DMA_Mem (ByVal memID As Long ) As Long @ Argument memID:...
  • Page 67 use an 8237-style DMA controller in the host computer and therefore it is not blocked in 64K maximal groups. PCI-7300A bus mastering works as follows: 1. To set up bus mastering, first do all normal PCI-7300A initialization necessary to control the board in status mode. This includes testing for the presence of the PCI BIOS, determining the base addresses, slot number, vendor and device ID's, I/O or memory, space allocation, etc.
  • Page 68 @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Start (int card_number, HANDLE memID, U32 count, int clear_fifo, int disable_di) Visual Basic (Windows 95) W_7300_DI_DMA_Start (ByVal card_number As Long, ByVal memID As Long, ByVal count As Long, ByVal clear_fifo As Long, ByVal disable_di As Long) As Long C/C++ (DOS) int _7300_DI_DMA_Start (int card_number, int mode, U32 *buffer, U32 count, int clear_fifo, int disable_di)

  • Page 69: 7300_Di_Dma_Status

    @ Return Code NoError PCICardNumErr PCICardNotInit DMATransferNotAllowed InvalidDIOCount BufNotDWordAlign DMADscrBadAlign 5.15 _7300_DI_DMA_Status @ Description Since the _7300_DI_DMA_Start function is executed in background, you can issue this function to check its operation status. @ Syntax Visual C/C++ (Windows 95) int W_7300_DI_DMA_Status (int card_number, int *status) Visual Basic (Windows 95) W_7300_DI_DMA_Status (ByVal card_number As Long, status As Long) As Long...

  • Page 70: 7300_Getoverrunstatus

    int _7300_DI_DMA_Stop (int card_number) @ Argument card_number: The card number of the PCI-7300A card. @ Return Code NoError PCICardNumErr PCICardNotInit 5.17 _7300_GetOverrunStatus @ Description When you use _7300_DI_DMA_Start to input data, the input data is stored in the FIFO of PCI controller. The data then transfer to memory through PCI-bus if PCI-bus is available.
  • Page 71 int W_7300_DO_DMA_Start (int card_number, HANDLE memID, U32 count) Visual Basic (Windows 95) W_7300_DO_DMA_Start (ByVal card_number As Long, ByVal memID As Long, ByVal count As Long) As Long C/C++ (DOS) int _7300_DO_DMA_Start (int card_number, U32 *buff, U32 count, int repeat, DMA_DSCR *dma_dscr_ptr) @ Argument card_number: The card number of the PCI-7300A card.

  • Page 72: 7300_Do_Dma_S Tatus

    5.19 _7300_DO_DMA_Status @ Description Since the _7300_DO_DMA_Start function is executed in background, you can issue the function _7300_DO_DMA_Status to check its operation status. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_DMA_Status (int card_number, int *status) Visual Basic (Windows 95) W_7300_DO_DMA_Status (ByVal card_number As Long, status As Long) As Long C/C++ (DOS) int _7300_DO_DMA_Status (int card_number, int *status)

  • Page 73: 7300_Do_Pg_S Tart

    PCICardNumErr PCICardNotInit 5.21 _7300_DO_PG_Start @ Description The function will perform pattern generation with the data stored in buff_ptr. It will takes place in the background which will not be stop until your program execute _7300_DO_PG_Stop function to stop the process. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_PG_Start (int card_number, void *buff_ptr, U32...

  • Page 74: 7300_Do_Pg_S Top

    5.22 _7300_DO_PG_Stop @ Description This function is used to stop the pattern generation operation. After executing this function, the _7300_DO_PG_Start function is stopped. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_PG_Stop (int card_number) Visual Basic (Windows 95) W_7300_DO_PG_Stop (ByVal card_number As Long) As Long C/C++ (DOS) int _7300_DO_PG_Stop (int card_number) @ Argument...

  • Page 75: 7300_Do_Timer

    @ Return Code NoError PCICardNumErr PCICardNotInit 5.24 _7300_DO_Timer @ Description This function is used to set the internal timer pacer for digital output. Timer pacer frequency = 10Mhz / C1. @ Syntax Visual C/C++ (Windows 95) int W_7300_DO_Timer (int card_number, U16 c1) Visual Basic (Windows 95) W_7300_DO_Timer (ByVal card_number As Long, ByVal c1 As Integer) As Long...

  • Page 76: 7300_G Et

    W_7300_Int_Timer (ByVal card_number As Long, ByVal c2 As Integer) As Long C/C++ (DOS) int _7300_Int_Timer (int card_number, U16 c2) @ Argument card_number: The card number of the PCI-7300A card. frequency divider of Counter #2. Valid value ranges from 2 to 65535. Note: Since the Integer type in Visual Basic is signed integer.

  • Page 77: 7300_S Et

    5.27 _7300_Set_Sample @ Description For the language without pointer support such as Visual Basic, programmer can use this function to write the output data to the index-th position in output DMA buffer. This function is only available in Windows 95 version. @ Syntax Visual C/C++ (Windows 95) int W_7300_Set_Sample (U32 linearAddr, U32 index, U32 data_value,...
  • Page 78 @ Argument card_number: The card number of the PCI-7300A card. underrun: 0: underrun sitation did not occur. 1: underrun situation occurred. @ Return Code NoError PCICardNumErr, PCICardNotInit C/C++ Libraries • 69...

  • Page 79: Appendix A 8254 Programmable Interval Timer

    Appendix A 8254 Programmable Interval Timer Note: The material of this section is adopted from “Intel Microprocessor and Peripheral Handbook Vol. II --Peripheral” A.1 The Intel (NEC) 8254 The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz.
  • Page 80 Before loading or reading any of these individual counters, the control byte (Base + C) must be loaded first. The format of control byte is: Control Byte: (Base + 7, Base + 11) • SC1 & SC1 - Select Counter (Bit7 & Bit 6) COUNTER ILLEGAL •...

  • Page 81: Mode Definition

    A.3 Mode Definition In 8254, there are six different operating modes can be selected. They are: • Mode 0: Interrupt on terminal count The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will count.
  • Page 82 • Mode 3: Square Wave Rate Generator. Similar to MODE 2 except that the output will remain high until one half the count has been completed (or even numbers) and go low for the other half of the count. This is accomplished by decrement the counter by two on the falling edge of each clock pulse.

  • Page 83: Warranty Policy

    Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the fo llowing carefully. Before using ADLINK’s products, please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form.
  • Page 84 To ensure the speed and quality of product repair, please download an RMA application form from our company website www.adlinktech.com Damaged products with RMA forms attached receive priority. For further questions, please contact our FAE staff. ADLINK: service@adlinktech.com Test & Measurement Product Segment: NuDAQ@adlinktech.com Automation Product Segment: Automation@adlinktech.com...

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