ADLINK Technology cExpress-KL User Manual
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ADLINK Technology cExpress-KL User Manual

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cExpress-KL
User's Manual
COM Express Compact Size Type 6 Module with
Mobile 7th Gen Intel® Core™ and Celeron® Processor
Leading EDGE COMPUTING
Manual Rev.:
1.1
Revision Date:
January 3, 2020
Part Number:
50-1J085-1010

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Summary of Contents for ADLINK Technology cExpress-KL

  • Page 1 User’s Manual COM Express Compact Size Type 6 Module with Mobile 7th Gen Intel® Core™ and Celeron® Processor Manual Rev.: Revision Date: January 3, 2020 Part Number: 50-1J085-1010 Leading EDGE COMPUTING...
  • Page 2 Preface Copyright © 2019-2020 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

  • Page 3: Table Of Contents

    Table of Contents Preface ..........................ii List of Figures ........................v List of Tables........................vi Introduction........................1 Specifications ......................3 2.1. Core System .......................3 2.2. Expansion Busses ......................3 2.3. Video........................... 4 2.4. Audio........................... 4 2.5. LAN..........................4 2.6. Multi I/O and Storage....................4 2.7. Serial I/O on Module (need BIOS RD help) ...............5 2.8.

  • Page 4: Preface

    4.6. BIOS Setup Defaults Reset Button................34 4.7. Switch Settings ......................35 Smart Embedded Management Agent (SEMA) .............37 5.1. Board Specific SEMA Functions................38 System Resources ....................41 6.1. System Memory Map....................41 6.2. Direct Memory Access Channels................41 6.3. I/O Map ........................41 6.4. Interrupt Request (IRQ) Lines...................43 6.5.

  • Page 5: List Of Figures

    List of Figures Figure 1: cExpress-KL Functional Block Diagram..................7 Figure 1: cExpress-KL Mechanical Drawing ....................8 Figure 1: cExpress-KL Connector, Switch and LED Locations ............. 29 Figure 1: cExpress-KL and the DB40 Debug Module ................29 Figure 1: cExpress Switch Locations ....................35 Figure 1: COM Express Mounting Methods ..................
  • Page 6 List of Tables Table 1: cExpress-KL AB/CD Pin Definitions ...................9 Table 1: 40-pin Debug Connector Pin Definition ................... 30 Table 1: cExpress-KL LED Descriptions ....................31 Table 1: XDP Debug Header Pin Definition ..................32 Table 1: Fan Connector Pin Definition ....................33 Table 1: BIOS Select and Mode Configuration Switch Settings............

  • Page 7: Introduction

    The cExpress-KL features a single onboard Gigabit Ethernet port, up to six PCIe Gen3 ports (build option), four USB 3.0 ports, four USB 2.0 ports, and three SATA 6Gb/s ports. Support is provided for SMBus and I C.
  • Page 8 This page intentionally left blank. Introduction...

  • Page 9: Specifications

    2. Specifications 2.1. Core System 7th Generation Intel® Core™ and Celeron® processor SoC (formerly “Kaby Lake U”) • Intel® Core™ i7-7600U 2.8 GHz (3.9 GHz Turbo), 15W (cTDP support) (2C/GT2) • Intel® Core™ i5-7300U 2.6 GHz (3.5 GHz Turbo), 15W (cTDP support) (2C/GT2) •...

  • Page 10: Video

    2.3. Video Intel® Generation 9 Low Power Graphics core architecture (Intel® HD Graphics 620/610) Integrated on Processor • GPU Feature Support 3 independent and simultaneous display combinations of DisplayPort/HDMI/LVDS/VGA monitors (eDP & VGA by build option, support by project basis) •...

  • Page 11: Serial I/O On Module (Need Bios Rd Help)

    2.7. Serial I/O on Module Chipset: Nuvoton NCT5104D Ports: 2x UARTs Rx/Tx only, the bit rate can support up to 115.2k bps Console Redirection: selectable in BIOS, supported during BIOS POST COM Port Description IRQ Address Console redirection support...

  • Page 12: Power Specifications

    2.11. Power Specifications AT and ATX mode (AT mode startup controlled by SEMA Board Controller) Power Modes ATX: 12V±5% / 5Vsb ±5% or AT = 12V±5% Standard Voltage Input ATX: 5-20 V / 5Vsb ±5% or AT = 5-20V Wide Voltage Input ACPI 5.0 compliant, Smart Battery support Power Management Supports C1-C6, S0, S3, S4, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5)

  • Page 13: Functional Diagram

    (port 0‐3) 3x SATA 6Gb/s (port 0/1) HD Audio UART0, UART1 UART LPC bus GPIO PCA9535 SPI 0 BIOS SMBus 4x GPO, 4x GPI SPI 1 BIOS GP I SEMA DDC I SPI_CS# LM73 Figure 1: cExpress-KL Functional Block Diagram Specifications...

  • Page 14: Mechanical Drawing

    Side View All are dimensions shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances of the module connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00]) should be ±0.10mm. Figure 2: cExpress-KL Mechanical Drawing Specifications...

  • Page 15: Pinouts And Signal Descriptions

    3.1. AB/CD Pin Definitions The cExpress-KL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector All pins in the COM Express specification are described, including those not supported on the cExpress-KL. Those not supported on the cExpress-KL module are crossed out.
  • Page 16 Row A Row B Row C Row D Name Name Name Name USB6- USB7- DDI1_PAIR3+ DDI3_CTRLCLK_AUX+ USB6+ USB7+ DDI1_PAIR3- DDI3_CTRLDATA_AUX- USB_6_7_OC# USB_4_5_OC# RSVD DDI3_DDC_AUX_SEL USB4- USB5- DDI3_PAIR0+ DDI2_PAIR0+ USB4+ USB5+ DDI3_PAIR0- DDI2_PAIR0- GND (FIXED) GND (FIXED) GND (FIXED) GND (FIXED) USB2- USB3- DDI3_PAIR1+...
  • Page 17 Row A Row B Row C Row D Name Name Name Name GND (FIXED) GND (FIXED) GND (FIXED) GND (FIXED) LVDS_A_CK+ LVDS_B_CK+ PEG_RX9+ PEG_TX9+ (eDP_TX3+) LVDS_A_CK- LVDS_B_CK- PEG_RX9- PEG_TX9- (eDP_TX3-) LVDS_I2C_CK LVDS_BKLT_CTRL RSVD RSVD /eDP_AUX+ * /eDP_BKLT_CTRL * LVDS_I2C_DAT...

  • Page 18: Signal Description Terminology

    3.2. Signal Description Terminology The following terms are used in the COM Express AB/CD Signal Descriptions below. Input to the Module Output from the Module Bi-directional input/output signal Open drain output I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant I 3.3Vsb Input 3.3V tolerant active in standby state O 3.3V...

  • Page 19: Ab Signal Descriptions

    3.3. AB Signal Descriptions 3.3.1. Audio Signals Signal Description PU/PD Comment AC_RST# / Reset output to codec, active low. O 3.3VSB HDA_RST# AC_SYNC / Sample-synchronization signal to the O 3.3V HDA_SYNC codec(s). Serial data clock generated by the AC_BITCLK / I/O 3.3V...
  • Page 20 3.3.3. LVDS/eDP Signal Description PU/PD Comment LVDS_A0+ LVDS Channel A differential pairs LVDS is default. LVDS_A0- LVDS (through eDP to LVDS_A1+ LVDS bridge) LVDS_A1- LVDS_A2+ Note: eDP support LVDS_A2- - LVDS_A3+ is a build option LVDS_A3- LVDS_A_CK+ LVDS Channel A differential clock LVDS_A_CK- LVDS LVDS_B0+...
  • Page 21 3.3.4. Gigabit Ethernet Gigabit Ethernet Description PU/PD Comment GBE0_MDI0+ Gigabit Ethernet Controller 0: Media Dependent Interface Twisted pair GBE0_MDI0- Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, Analog signals for GBE0_MDI1+ 100, and 10Mbit/sec modes. Some pairs are unused in...
  • Page 22 3.3.6. PCI Express Signal Description PU/PD Comment PCIE_TX0+ PCI Express channel 0, Transmit Output O PCIE AC coupled on Module PCIE_TX0- differential pair. PCIE_RX0+ PCI Express channel 0, Receive Input I PCIE AC coupled off Module PCIE_RX0- differential pair. PCIE_TX1+ PCI Express channel 1, Transmit Output O PCIE AC coupled on Module...
  • Page 23 3.3.8. LPC Bus Signal Description PU/PD Comment LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data Skylake platform uses 3.3VSB standby power for LPC LPC_FRAME# LPC frame indicates the start of an LPC cycle Skylake platform uses 3.3VSB standby power for LPC...
  • Page 24 Signal Description PU/PD Comment USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. PU 10k Do not pull high on carrier A pull-up for this line shall be present on the 3.3VSB 3.3VSB module. An open drain driver from a USB current monitor on the carrier board may drive this line low.
  • Page 25 3.3.12. Miscellaneous Signal Description PU/PD Comment SPKR Output for audio enunciator, the “speaker” in O 3.3V PC-AT systems Output indicating that a watchdog time-out O 3.3V event has occurred. THRM# Input from off-module temp sensor I 3.3V indicating an over-temp situation.
  • Page 26 3.3.15. General Purpose I/O (GPIO) Signal Description PU/PD Comment GPO[0] General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET output GPO[1] General purpose output pins. O 3.3V PU 10K 3.3V After hardware RESET output GPO[2] General purpose output pins. O 3.3V PU 10K 3.3V After hardware...
  • Page 27 3.3.17. Power and System Management Signal Description PU/PD Comment PWRBTN# Power button to bring system out of S5 (soft off), active on I 3.3VSB PU 10k falling edge. 3.3VSB SYS_RESET# B49 Reset button input. Active low request for module to reset I 3.3VSB...
  • Page 28 3.3.18. Power and Ground Signal Description PU/PD Comment VCC_12V A104-A109 Primary power input: +12V nominal (5 ~ 20V wide 5-20 V input). B104-B109 All available VCC_12V pins on the connector(s) shall be used. VCC_5V_SBY B84-B87 Standby power input: +5.0V nominal. If VCC5_SBY 5Vsb ±5% is used, all available VCC_5V_SBY pins on the connector(s) shall be used.

  • Page 29: Cd Signal Descriptions

    3.4. CD Signal Descriptions 3.4.1. USB 3.0 extension Signal Description PU/PD Comment USB_SSRX0- Additional Receive signal differential pairs for the I PCIE AC coupled off USB_SSRX0+ SuperSpeed USB data path on USB0 Module USB_SSTX0- Additional Transmit signal differential pairs for the...
  • Page 30 3.4.3. DDI Channels DDI 1 Signal Description PU/PD Comment DDI1_PAIR0+ Digital Display Interface1 differential O PCIE Pair 4 to Pair 6 pairs DDI1_PAIR0- Not supported DDI1_PAIR1+ DDI1_PAIR1- DDI1_PAIR2+ DDI1_PAIR2- DDI1_PAIR3+ DDI1_PAIR3- DDI1_PAIR4+ DDI1_PAIR4- DDI1_PAIR5+ DDI1_PAIR5- DDI1_PAIR6+ DDI1_PAIR6- DDI1_HPD Digital Display Interface Hot-Plug I PCIE Detect 100K...
  • Page 31 DDI 2 Signal Description PU/PD Comment DDI2_PAIR0+ Digital Display Interface2 differential pairs DDI2_PAIR0- DDI2_PAIR1+ DDI2_PAIR1- DDI2_PAIR2+ DDI2_PAIR2- DDI2_PAIR3+ DDI2_PAIR3- DDI2_HPD 100K DDI2_CTRLCLK_AUX+ IF DDI2_DDC_AUX_SEL is floating I/O PCIe DP2_AUX+, AC 100K coupled on Module IF DDI2_DDC_AUX_SEL pulled high I/O OD HDMI2_CTRLCLK 3.3V...
  • Page 32 3.4.4. DDI to DP/HDMI/SDVO Mapping Pin Name HDMI \ DVI DDI1_PAIR0+ DP1_LANE0+ TMDS1_DATA2+ DDI1_PAIR0- DP1_LANE0- TMDS1_DATA2- DDI1_PAIR1+ DP1_LANE1+ TMDS1_DATA1+ DDI1_PAIR1- DP1_LANE1- TMDS1_DATA1- DDI1_PAIR2+ DP1_LANE2+ TMDS1_DATA0+ DDI1_PAIR2- DP1_LANE2- TMDS1_DATA0- DDI1_PAIR3+ DP1_LANE3+ TMDS1_CLK+ DDI1_PAIR3- DP1_LANE3- TMDS1_CLK- DDI1_PAIR4+ Not supported Not supported DDI1_PAIR4- Not supported Not supported DDI1_PAIR5+...
  • Page 33 3.4.5. PCI Express Graphics x16 (no PEG support) Signal Description PU/PD Comment PEG_RX0+ PCI Express Graphics transmit differential I PCIE Not supported PEG_RX0- pairs. PEG_RX1+ PEG_RX1- PEG_RX2+ PEG_RX2- PEG_RX3+ PEG_RX3- PEG_RX4+ PEG_RX4- PEG_RX5+ PEG_RX5- PEG_RX6+ PEG_RX6- PEG_RX7+ PEG_RX7- PEG_RX8+...
  • Page 34 Signal Description PU/PD Comment PEG_TX15+ D101 PEG_TX15- D102 PEG_LANE_RV# D54 PCI Express Graphics lane reversal input I 1.05V Not supported strap. Pull low on the Carrier board to reverse lane order. 3.4.6. Module Type Definition Signal Description Comment TYPE0# The TYPE pins indicate to the Carrier Board the Pin-out Type that is Type 6 TYPE1# implemented on the module.

  • Page 35: Connector Pinouts On Module

    CPU BIOS Defaults Reset Button 40-pin Debug 4-pin Connector Figure 3: cExpress-KL Connector, Switch and LED Locations cExpress-KL and the DB40 Debug Module sFor illustration purposes only Figure 4: cExpress-KL and the DB40 Debug Module Connector Pinouts on Module...

  • Page 36: 40-Pin Debug Connector

    4.2. 40-pin Debug Connector FPC Connector Type: FCI 59GF Flex 10042867 Pin Orientation 40-pin Debug Connector Pin Definition on the COM Express Module Interface Signal Remark Interface Signal Remark VCC_SPI_IN SPI Power Input from flash TXD6 Program tool to module. HW need add Program interface MOS FET to switch SPI power...

  • Page 37: Status Leds

    Rebooted after PWRBTN WD LED = LED OFF Rebooted after RESET BTN WD LED = LED OFF Note: only a RESET not initiated by the BMC can clear the WD LED (user action) Table 3: cExpress-KL LED Descriptions Connector Pinouts on Module...

  • Page 38: Xdp Debug Header

    4.4. XDP Debug Header The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector. XDP Signal Target Signal Device XDP Signal...

  • Page 39: Fan Connector

    4.5. Fan Connector Connector Type: JVE 24W1125A-04M00 Pin Orientation 1 2 3 4 Pin Assignment Name Signal Description BMC_FAN_OUT FAN_PWMOUT BMC_FAN_PWM_IN FAN_TACHIN Ground P5V_S Table 5: Fan Connector Pin Definition Connector Pinouts on Module...

  • Page 40: Bios Setup Defaults Reset Button

    4.6. BIOS Setup Defaults Reset Button To perform a hardware reset of BIOS default settings, perform the following steps: 1. Shut down the system. 2. Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears 3.

  • Page 41: Switch Settings

    4.7. Switch Settings Switch Locations BIOS Select and Mode Configuration Switch Figure 5: cExpress Switch Locations BIOS Select and Mode Configuration Switch The module has two BIOS chips and BIOS operation can be configured to "PICMG" and dual-BIOS "Failsafe"...
  • Page 42 This page intentionally left blank. Connector Pinouts on Module...

  • Page 43: Smart Embedded Management Agent (Sema)

    5. Smart Embedded Management Agent (SEMA) The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented: ‧ Total operating hours counter. Counts the number of hours the module has been run in minutes.

  • Page 44: Board Specific Sema Functions

    5.1.2. Main Current The BMC of the cExpress-KL implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board.
  • Page 45 5.1.4. Exception Codes In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed.
  • Page 46 This page intentionally left blank. Smart Embedded Management Agent (SEMA)

  • Page 47: System Resources

    6. System Resources 6.1. System Memory Map Address Range (decimal) Address Range (hex) Size Description (4GB-2MB) FFE00000 – FFFFFFFF 16 MB High BIOS Area (4GB-18MB) – (4GB-17MB-1) FEE00000 – FEEFFFFF 1 MB MSI Interrupts (4GB-20MB) – (4GB-19MB-1) FEC00000 – FECFFFFF...
  • Page 48 Hex Range Device 52h – 53h Timer/Counter LPC/eSPI NMI Controller Microcontroller NMI Controller1 Microcontroller NMI Controller1 Microcontroller NMI Controller1 RTC Controller RTC Controller RTC Controller RTC Controller RTC Controller RTC Controller 76h – 77h RTC Controller LPC/eSPI or PCIe 84h – 86h Reserved Reserved 8Ch –...

  • Page 49: Interrupt Request (Irq) Lines

    6.4. Interrupt Request (IRQ) Lines PIC Mode IRQ# Typical Intterupt Resource Connected to Pin Available Counter 0 Keyboard controller Cascade interrupt from slave PIC Serial Port 4 (COM4) IRQ3 via SERIRQ / PIRQ Note (1) Serial Port 3 (COM3)

  • Page 50: Pci Configuration Space Map

    IRQ# Typical Intterupt Resource Connected to Pin Available Secondary IDE controller IRQ15 via SERIRQ / PIRQ Note (1) P.E.G Root Port,Intel HDA, PCIE Port Note (1) 0/1/2/3/4/5/6, EHCI Conterller #2 , I.G.D ,XHCI Controller PCIE Port 0/1/2/3/4/5/6, P.E.G Root Note (1) Port, PCIE Port 0/1/2/3/4/5/6, P.E.G Root Note (1)
  • Page 51 Device: Functions # Function Description Bus 0: Device 28: Function 3 PCI Express Port 4 Bus 0: Device 28: Function 4 PCI Express Port 5 Bus 0: Device 28: Function 5 PCI Express Port 6 Bus 0: Device 28: Function 6...

  • Page 52: Pci Interrupt Routing Map

    6.6. PCI Interrupt Routing Map P.E.G. Root Audio xHCI Controller ME Controller ME Controller IDE-R Line Port Controller Int0 INTA:16 INTA:16 INTA:16 INTA:16 Int1 INTB:17 INTD:17 Int2 INTC:18 INTC:18 Int3 INTD:19 INTB:19 PCIE port1 PCIE port 2 PCIE port 3 PCIE port 4 PCIE port5 Line...

  • Page 53: Bios Setup

    7. BIOS Setup 7.1. Menu Structure This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item.

  • Page 54: Main

    7.2. Main The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings. 7.2.1.
  • Page 55 7.2.3.1. PCH Information System Management Feature Options Description System Management Info only Version Info only Display version. 7.2.4. System Management 7.2.4.1. System Management > Board Information Board Information Info only Description SMC Firmware Read only Display SMC Firmware. Build Date Read only Display SMC firmware build date.
  • Page 56 7.2.4.3. System Management > Power Consumption Feature Options Description Power Consumption Info only Current Input Current Read only Display input current. Current Input Power Read only Display input power. VCORE Read only Display actual voltage of the VCORE. VGFX Read only Display actual voltage of the VCORE.
  • Page 57 7.2.4.5. System Management > Flags Feature Options Description Flags Info only BMC Flags Read only BIOS Select Read only Display the selection of current BIOS ROM. ATX/AT-Mode Read only Display ATX/AT-Mode. Exception Code Read only System exception reason. 7.2.4.6. System Management > Power Up...
  • Page 58 7.2.5. System Date and Time Feature Options Description Weekday, Requires the alpha-numeric entry of the day of the System Date MM/DD/YYYY week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX) System Time HH/MM/SS...

  • Page 59: Advanced

    7.3. Advanced This menu contains the settings for most of the user interfaces in the system. 7.3.1. Feature Options Description Info only Manufacturer, model, speed CPU Signature Info only Display CPU Signature. Microcode Revision Info only Display Microcode Patch.
  • Page 60 Feature Options Description C-State Auto Demotion Disabled Configure C-State Auto Demotion C1 and C3 Package C State limit Package C State limit Auto CPU Default C0/C1 Enables utilization of additional hardware capabilities Intel Trusted Execution Technology Disabled provided by Intel® Trusted Execution Technology. Enabled Changes require a full power cycle to take effect.
  • Page 61 7.3.2. Memory Feature Options Description Memory RC Version Info only Display Memory Reference Code Version. Memory Frequency Info only Display Memory Frequency. Total Memory Info only Display Total Memory. Memory Timings Info only Display Memory Timings Channel 0/1 slot Info only Display Memory Size.
  • Page 62 7.3.3. Graphics Feature Options Description Graphics Configuration Info only IGFX VBIOS Version Info only Display VBIOS Version. Graphics Turbo IMON Current Number entry field Graphics turbo IMON current values supported (14-31). Primary Display Select which of IGFX//PCIE Graphics device should be Auto Primary Display..
  • Page 63 Feature Options Description Hsync Polarity Hsync Polarity select Active High Active Low LVDS Backlight Mode Select LVDS Backlight control function. BMC Mode GTT Mode GTT LVDS/eDP Backlight Control Set VBIOS Brightness. Range::0-255. DDI port 1 No device Select DDI port 1 function: DisplayPort or HDMI.
  • Page 64 7.3.4. SATA Feature Options Description SATA Controller(s) Enable/Disable SATA Device. Enabled Disabled SATA Mode Selection Determines how SATA controller(s) operate. AHCI Intel RST Premium SATA Test Mode Enabled Test Mode Enable/Disable (Loop Back) Disabled Software Feature Mask Configuration Submenu Aggressive LPM Support Enable PCH to aggressively enter link power state.
  • Page 65 7.3.4.2. SATA > Software Feature Mask Configuration Feature Options Description HDD Unlock If enabled, indicates that the HDD password unlock Enabled in the OS is enabled. Disabled LED Locate If enabled, indicates that the LED/SGPIO hardware Enabled is attached and ping to locate feature is enabled on Disabled the OS.
  • Page 66 7.3.5.1. USB > USB Configuration Feature Options Description XHCI Disable Compliance Mode Options to disable Compliance Mode. Default is FALSE FALSE to not disable Compliance Mode. Set TRUE TRUE to disable Compliance Mode. XDCI Support Enable/Disable XDCI (USB OTG Device) Disabled Enabled USB Port Disable Override...
  • Page 67 Feature Options Description CIRA Timeout OEM defined timeout for MPS connection to be established. 0 - use the default timeout value of 60 seconds. 255 - MEBX waits until the connection succeeds. Watchdog Enabled Enable/Disable WatchDog Timer. Disabled OS Timer Set OS watchdog timer.
  • Page 68 7.3.7.1. PCI and PCIe > PCI Express Configuration Feature Options Description PCI Express Configuration Info only PCI Express Clock Gating Disabled Enable/Disable PCI Express Clock Gating for each root port. Enable DMI Link ASPM Control The control of Active State Power Management of Disabled the DMI Link.Auto is equal to POR setting.
  • Page 69 Feature Options Description PCI Express Unsupported Request Reporting Disabled Enable/Disable. Enable PCI Express Device Fatal Error Reporting Disabled Enable/Disable. Enable NFER PCI Express Device Non-Fatal Error Reporting Disabled Enable/Disable. Enable PCI Express Device Correctable Error Reporting Disabled Enable/Disable. Enable...
  • Page 70 Feature Options Description Non Snoop Latency Ocerrid Disabled Non Snoop Latency Override for PCH PCIE. Manual Disabled: Disable override.Manual: Manually enter override values. Auto Auto (default): Maintain default BIOS flow. Force LTR Override Force LTR Override for PCH PCIE.Disabled: Disable LTR override values will not be forced.Enable: Enable LTR override values will be forced and LTR...
  • Page 71 Feature Options Description N5104D Super IO Configuration Info only Serial Port 1 Configuration Serial Port Enable/Disable Serial Port (COM). Enabled Disabled IO=240h; IRQ=7 Device Settings Fixed configuration of serial port. Auto Change Settings Select an optimal setting for Super IO IO=240h;...
  • Page 72 7.3.10. Sound Feature Options Description Sound Info only HD Audio Disabled Control Detection of the HD-Audio device. Enabled Disabled: HDA will be unconditionally disabled. Enabled: HDA will be unconditionally enabled. Auto Auto: HDA will be enabled if present, disabled otherwise. 7.3.11.
  • Page 73 Feature Options Description Parity Select Parity. None Even Mark Space Stop Bits Select number of stop bits. Flow Control Select flow control. None Hardware RTS/CTS VT-UTF8 Combo Key Support Disabled Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals. Enable Recorder Mode With this mode enabled only text will be sent.
  • Page 74 Feature Options Description Bits per second 9600 Selects serial port transmission speed. 19200 The speed must be matched on the other side. Long or noisy lines may require lower speeds. 38400 57600 115200 Flow Control Flow control can prevent data loss from buffer None overflow.
  • Page 75 7.3.14. Miscellaneous Feature Options Description Trusted Computing Submenu NVME Configuration Submenu 7.3.14.1. Miscellaneous > Trusted Computing Feature Options Description Security Device Support Enabled Enables or Disables BIOS support for security device. When disabled OS wil not show Security Disabled Device.
  • Page 76 7.3.14.3. Miscellaneous > NVME Configuration Feature Options Description NVME controller and Drive information Info Only 7.3.15. AMI Graphics Output Protocol Policy (Video GOP show only) Feature Options Description Intel(R) Graphics Controller Info only Intel(R) GOP Driver Info only Output Select Output Interface DVT1 BIOS Setup...

  • Page 77: Security

    7.4. Security 7.4.1. Password Description Feature Options Description Administrator Password Enter password User Password Enter password HDD Security Configuration: Info only Px: xxxxxxxx Info only Secure Boot Submenu Customizable Secure Boot settings 7.4.1.1. Secure Boot Feature Options Description System Mode...

  • Page 78: Boot

    7.5. Boot 7.5.1. Boot Configuration Feature Options Description Boot Configuration Info only Setup Prompt Timeout Enable/Disable the onboard SATA controllers. Bootup NumLock State Select SATA controller mode. Enable/Disable the PATA port. In fact this enables or Quiet Boot Disabled disables the SATA channel on which the onboard SATA Enabled to PATA converter is attached.
  • Page 79 7.5.1.1. CSM Configuration Feature Options Description CSM Support This option controls if CSM will be launched. Enabled Disable CSM16 Module Version Info only GateA20 Active UPON REQUEST: GA20 can be disabled using BIOS Upon Request services. ALWAYS: do not allow disabling GA20; this Always option is useful when any RT code is executed above 1MB.

  • Page 80: Save & Exit

    7.6. Save & Exit 7.6.1. Save Options Feature Options Description Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save Changes and Reset Reset the system after saving the changes. Discard Changes and Reset Reset system setup without saving any changes.

  • Page 81: Bios Checkpoints, Beep Codes

    8. BIOS Checkpoints, Beep Codes This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.

  • Page 82: Status Code Ranges

    8.1. Status Code Ranges Status Code Description Range 0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors 0x10 – 0x2F PEI execution up to and including memory detection 0x30 – 0x4F PEI execution after memory detection 0x50 – 0x5F PEI errors 0x60 –...
  • Page 83 SEC Error Codes 0x0C – 0x0D Reserved for future AMI SEC error codes 0x0E Microcode not found 0x0F Microcode not loaded 8.2.2. SEC Beep Codes None 8.2.3. PEI Phase Status Code Description Progress Codes 0x10 PEI Core is started...
  • Page 84 Status Code Description 0x35 CPU post-memory initialization. Boot Strap Processor (BSP) selection 0x36 CPU post-memory initialization. System Management Mode (SMM) initialization 0x37 Post-Memory North Bridge initialization is started 0x38 Post-Memory North Bridge initialization (North Bridge module specific) 0x39 Post-Memory North Bridge initialization (North Bridge module specific) 0x3A Post-Memory North Bridge initialization (North Bridge module specific) 0x3B...
  • Page 85 Status Code Description S3 Resume Error Codes 0xE8 S3 Resume Failed 0xE9 S3 Resume PPI not Found 0xEA S3 Resume Boot Script Error 0xEB S3 OS Wake Error 0xEC-0xEF Reserved for future AMI error codes Recovery Progress Codes 0xF0...
  • Page 86 8.2.5. DXE Status Codes Status Code Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64 CPU DXE initialization (CPU module specific) 0x65 CPU DXE initialization (CPU module specific) 0x66 CPU DXE initialization (CPU module specific) 0x67...
  • Page 87 Status Code Description 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization is started 0x9B USB Reset 0x9C USB Detect 0x9D USB Enable 0x9E –...
  • Page 88 Status Code Description 0xB8 – 0xBF Reserved for future AMI codes 0xC0 – 0xCF OEM BDS initialization codes DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 South Bridge initialization error 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error.

  • Page 89: Oem-Reserved Checkpoint Ranges

    Status Code Description 0x10 System is waking up from the S1 sleep state 0x20 System is waking up from the S2 sleep state 0x30 System is waking up from the S3 sleep state 0x40 System is waking up from the S4 sleep state 0xAC System has transitioned into ACPI mode.
  • Page 90 This page intentionally left blank. BIOS Checkpoints, Beep Codes...

  • Page 91: Mechanical Information

    9. Mechanical Information 9.1. Board-to-Board Connectors To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When 5 mm receptacles are chosen, the carrier board should be free of components.

  • Page 92: Thermal Solution

    9.2. Thermal Solution 9.2.1. Heat Spreaders The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.
  • Page 93 Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module. Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown. Then press down on the module until it is firmly seated on the carrier board.
  • Page 94 Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown. Mechanical Information...

  • Page 95: Mounting Methods

    9.3. Mounting Methods There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of 5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting.

  • Page 96: Standoff Types

    9.4. Standoff Types The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and through-hole standoffs are SMT type. Other types not listed are available upon request. 5mm through-hole standoff (SMT type) 5mm threaded standoff (DIP type) P/N: 33-72000-0050 P/N: 33-72016-0050...

  • Page 97: Safety Instructions

    Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use. • Please read these safety instructions carefully. • Please keep this User‘s Manual for later reference.

  • Page 98: Getting Service

    5215 Hellyer Avenue, #110, San Jose, CA 95138, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-360-0222 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com...

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