ADLINK Technology cExpress-KL User Manual page 23

3.3.8. LPC Bus
Signal Pin
LPC_AD[0:3] B4-B7
LPC_FRAME# B3
LPC_DRQ0# B8
LPC_DRQ1# B9
LPC_SERIRQ A50
LPC_CLK B10
3.3.9. USB
Signal Pin
USB0+ A46
USB0- A45
USB1+ B46
USB1- B45
USB2+ A43
USB2- A42
USB3+ B43
USB3- B42
USB4+ A40
USB4- A39
USB5+ B40
USB5- B39
USB6+ A37
USB6- A36
USB7+ B37
USB7- B37
USB_0_1_OC# B44
USB_2_3_OC# A44
Pinouts and Signal Descriptions
Description
LPC multiplexed address, command and data
bus
LPC frame indicates the start of an LPC cycle
LPC serial DMA request
LPC serial interrupt
LPC clock output - 33MHz nominal
Description
USB differential data pairs for Port 0
USB differential data pairs for Port 1
USB differential data pairs for Port 1
USB differential data pairs for Port 2
USB differential data pairs for Port 3
USB differential data pairs for Port 4
USB differential data pairs for Port 5
USB differential data pairs for Port 6
USB over-current sense, USB ports 0 and 1.
A pull-up for this line shall be present on the
module. An open drain driver from a USB
current monitor on the carrier board may
drive this line low.
USB over-current sense, USB ports 2 and 3.
A pull-up for this line shall be present on the
module. An open drain driver from a USB
current monitor on the carrier board may
drive this line low. .
I/O PU/PD Comment
I/O Skylake platform uses
3.3VSB standby power for LPC
bus
O Skylake platform uses
3.3VSB standby power for LPC
bus
I 3.3V NC.
No support on Skylake-U
platform
I/O OD PU 8k2 Skylake platform uses
3.3VSB 3.3V standby power for LPC
bus.
O Skylake platform uses
3.3VSB standby power for LPC
bus.
The LPC_CLK frequency
is 24MHz.
I/O PU/PD Comment
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I/O USB 1.1/ 2.0 compliant
3.3VSB
I PU 10k Do not pull high on carrier
3.3VSB 3.3VSB
I PU 10k Do not pull high on carrier
3.3VSB 3.3VSB
cExpress-KL
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