ADLINK Technology cExpress-AR User Manual

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cExpress-AR User's Guide

cExpress-AR

Page 1

User's Guide

Revision:

Rev. 1.2

Date:

2021-08-31

Part Number:

50M-00014-1020

PICMG COM.0 R3.0

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Summary of Contents for ADLINK Technology cExpress-AR

Page 2: Revision History
User’s Guide PICMG COM.0 R3.0 Revision History Revision Description Date Author Initial release 2021-05-17 Update specifications, AB/CD Connector Signal Descriptions 2021-08-03 Remove Yocto Linux support 2021-08-31 Page 2 Copyright © 2021 ADLINK Technology, Inc.
Page 3: Preface
Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. Copyright © 2021 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Page 4 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. • Page 4 Copyright © 2021 ADLINK Technology, Inc.
Page 5 Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Page 5 Copyright © 2021 ADLINK Technology, Inc.
Page 6 ADLINK Technology GmbH Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. Page 6 Copyright © 2021 ADLINK Technology, Inc.
Page 7: Table Of Contents
Audio ..................................................................24 4.3.2 Analog VGA................................................................25 4.3.3 LVDS or eDP...............................................................26 4.3.4 Gigabit Ethernet ...............................................................29 4.3.5 SATA ..................................................................30 4.3.6 PCI Express .................................................................31 4.3.7 LPC bus ................................................................33 4.3.8 USB..................................................................34 4.3.9 SPI Bus (BIOS only) ............................................................36 Page 7 Copyright © 2021 ADLINK Technology, Inc.
Page 8 7.1. Operating Systems ..............................................................66 8. Mechanical and Thermal........................................................67 8.1. Module Dimensions ..............................................................67 8.2. Thermal Solutions ................................................................68 8.2.1 Heatspreader: HTS............................................................68 8.2.2 Heatsink: THS ..............................................................69 8.2.3 Heatsink High Profile: THSH ........................................................70 8.2.4 Heatsink with Fan: THSF ..........................................................71 Page 8 Copyright © 2021 ADLINK Technology, Inc.
Page 9: List Of Figures
Figure 1 – Module function diagram......................................................17 Figure 2 - Module rear side row and pin numbering ..............................................18 Figure 3 – Module feature locations.......................................................58 Figure 4 – cExpress-AR and Debug Module ..................................................59 Figure 5 – Module mechanical dimensions ..................................................67 Figure 6 – Heatspreader HTS ........................................................68 Figure 7 –...
Page 10: Introduction
Warning: this is an EA (early available) engineering manual, meaning contents may not properly reflect the actual or final version of this product The cExpress-AR is the first COM Express® COM.0 R3.0 Compact Size Type 6 module based on Octa-core (8 core) AMD® New Generation Ryzen™...
Page 11: Specifications
ECC, non-ECC support Cache L2 Cache 4MB for V2748, V2718, 3MB for V2546, V2516 Embedded BIOS AMI Aptio V UEFI with CMOS backup in 16MB SPI BIOS (dual BIOS by build option, project basis) Page 11 Copyright © 2021 ADLINK Technology, Inc.
Page 12: Video
DDI x 3: Digital Display Ports (DDI) support DisplayPort 1.4a, HDMI 2.1 or DVI, max. resolution of Display Port 4096x2160 @60Hz, max. resolution of HDMI 4096x2160 @60Hz VGA: VGA BOM option support, in place of DDI 3. Max. resolution is 1920x1200 @60Hz Note: The achievable maximum resolution dependent on carrier design. Page 12 Copyright © 2021 ADLINK Technology, Inc.
Page 13: Audio
IT version supports up to 2.5Gbits (supports TSN on Linux, by project basis, TBC) Note: General Purpose Ports GPP 2-9 can support up to 6 devices (SATA 0/1 count as one device), refer to Functional Diagram for details. Page 13 Copyright © 2021 ADLINK Technology, Inc.
Page 14: Multi I/O And Storage
4 GPO and 4 GPI (GPI with interrupt) SATA 2x SATA 6Gb/s (SATA 0,1) Note: General Purpose Ports GPP 2-9 can support up to 6 devices (SATA 0/1 count as one device), refer to Functional Diagram for details. Page 14 Copyright © 2021 ADLINK Technology, Inc.
Page 15: Trusted Platform Module (Tpm)
Power States: C1-C6, S0, S1, S3, S4, S5, S5 ECO mode (Wake-on-USB S3/S4, WoL S3/S4/S5) ECO Mode support for deep S5 for 5Vsb power saving Power Consumption Please contact your ADLINK representative for the document “COM Express Module Power Consumption”. Page 15 Copyright © 2021 ADLINK Technology, Inc.
Page 16: Mechanical And Environmental
Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27 MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D HALT tested Thermal Stress, Vibration Stress, Thermal Shock and Combined Test Page 16 Copyright © 2021 ADLINK Technology, Inc.
Page 17: Block Diagram
PCIe 24-27 TPM 2.0 DDR4 SODIMM (top side) PCIe 28-31 GPIO/SDIO 3200 MT/s, non-ECC/ECC Embedded Controller TM102 UART/CAN DDR4 SODIMM (bottom side) (board) 3200 MT/s, non-ECC/ECC LPC/eSPI Figure 1 – Module function diagram Page 17 Copyright © 2021 ADLINK Technology, Inc.
Page 18: Pinout And Signal Descriptions
The table below is a comprehensible list of all signal pins supported on the dual 220-pin COM Express connectors as defined for Type 6 in the PICMG COM.0 R3.0 specification. Signals described in the specification but not supported on the cExpress-AR are strikethrough STRIKETHROUGH.
Page 19 AC/HDA_SYNC AC/HDA_SDIN1 DDI1_PAIR5+ DDI1_PAIR1+ AC/HDA_RST# AC/HDA_SDIN0 DDI1_PAIR5- DDI1_PAIR1- GND (FIXED) GND (FIXED) GND (FIXED) GND (FIXED) AC/HDA_BITCLK SPKR DDI2_CTRLCLK_AUX+ DDI1_PAIR2+ AC/HDA_SDOUT I2C_CK DDI2_CTRLDATA_AUX- DDI1_PAIR2- BIOS_DIS0#/ESPI_SAFS I2C_DAT DDI2_DDC_AUX_SEL DDI1_DDC_AUX_SEL THRMTRIP# THRM# RSVD RSVD Page 19 Copyright © 2021 ADLINK Technology, Inc.
Page 20 RSVD RSVD PCIE_TX1+ PCIE_RX1+ RSVD RSVD PCIE_TX1- PCIE_RX1- PEG_RX4+ PEG_TX4+ WAKE0# PEG_RX4- PEG_TX4- GPI2 WAKE1# RAPID_SHUTDOWN PCIE_TX0+ PCIE_RX0+ PEG_RX5+ PEG_TX5+ PCIE_TX0- PCIE_RX0- PEG_RX5- PEG_TX5- GND (FIXED) GND (FIXED) GND (FIXED) GND (FIXED) Page 20 Copyright © 2021 ADLINK Technology, Inc.
Page 21 D101 PEG_TX15+ A102 SER1_RX/CAN_RX B102 FAN_TACHIN C102 PEG_RX15- D102 PEG_TX15- A103 LID# B103 SLEEP# C103 D103 A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V Page 21 Copyright © 2021 ADLINK Technology, Inc.
Page 22 (in place of LVDS) and VGA (in place of DDI 3) are BOM option support by project basis. General Purpose Ports GPP 2-9 can support up to a maximum of 6 devices (SATA 0/1 count as one device). Page 22 Copyright © 2021 ADLINK Technology, Inc.
Page 23: Signal Terminology Descriptions
Pull-down strap. A Module output pin that is either tied to GND or is not connected. Used to signal Module capabilities to the Carrier Board. PU (pull-up) resistor on module PD (pull-down) resistor on module Page 23 Copyright © 2021 ADLINK Technology, Inc.
Page 24: Ab Connector Signal Descriptions
Serial data clock generated by the external CODEC(s). I/O 3.3V HDA_BITCLK AC_SDOUT / Serial TDM data output to the CODEC. O 3.3V HDA_SDOUT AC_SDIN[2:0] / B28- B30 Serial TDM data inputs from up to 3 CODECs. HDA_SDIN[2:0] 3.3VSB Page 24 Copyright © 2021 ADLINK Technology, Inc.
Page 25: Analog Vga
I/O OD 3.3V PU 2k2 3.3V monitor capabilities) VGA_I2C_DAT DDC data line. I/O OD 3.3V PU 2k2 3.3V Note: VGA is BOM option support (in place of DDI 3) by project basis. Page 25 Copyright © 2021 ADLINK Technology, Inc.
Page 26: Lvds Or Edp
LVDS_B0+ LVDS_B0- LVDS_B1+ LVDS_B1- LVDS_B2+ LVDS_B2- LVDS_B3+ LVDS_B3- LVDS_B_CK+ LVDS_B_CK- LVDS_VDD_EN eDP_VDD_EN LVDS_BKLT_EN eDP_BKLT_EN LVDS_BKLT_CTRL eDP_BKLT_CTRL LVDS_I2C_CK eDP_AUX+ LVDS_I2C_DAT eDP_AUX- eDP_HPD Note: LVDS is default mode and eDP is a BOM option Page 26 Copyright © 2021 ADLINK Technology, Inc.
Page 27 LVDS_I2C_CK DDC lines used for flat panel detection and control. I/O OD 3.3V PU 2.2K 3.3V LVDS_I2C_DAT DDC lines used for flat panel detection and control. I/O OD 3.3V PU 2.2K 3.3V Page 27 Copyright © 2021 ADLINK Technology, Inc.
Page 28 I/O PCIE AC coupled off module eDP_HPD Detection of Hot Plug / Unplug and notification of the I 3.3V PD 100K PD 100K on this pin when eDP is supported link layer Page 28 Copyright © 2021 ADLINK Technology, Inc.
Page 29: Gigabit Ethernet
250 mA or less. GBE0_SDP Gigabit Ethernet Controller 0 Software-Definable Pin. Can also be used for IO 3.3VSB IEEE1588 support such as 1pps signal. Note: LAN LED behaviour is TBC. Page 29 Copyright © 2021 ADLINK Technology, Inc.
Page 30: Sata
GPP 8 SATA1 GPP 9 SATA2 Not supported SATA3 Not supported Note: General Purpose Ports GPP 2-9 can support up to a maximum of 6 devices (SATA 0/1 count as one device). Page 30 Copyright © 2021 ADLINK Technology, Inc.
Page 31: Pci Express
PCIE_RX5- PCIE_CLK_REF+ PCI Express Reference Clock output for all PCI Express and PCI O PCIE PCIE_CLK_REF- Express Graphics Lanes. Note: PCIe Lane 6, 7 are supported by PCIe switch, by project basis. Page 31 Copyright © 2021 ADLINK Technology, Inc.
Page 32 Notes: General Purpose Ports GPP 2-9 can support up to a maximum of 6 devices (SATA 0/1 count as one device). PCIe 0-3 can be x4, x2 or x1, PCIe 4-5 can be x2 or x1. Page 32 Copyright © 2021 ADLINK Technology, Inc.
Page 33: Lpc Bus
LPC_DRQ1 is not connected LPC_DRQ1# LPC_SERIRQ LPC serial interrupt I/O 3.3V Chipset has internal PU, 50K ±30% LPC_CLK LPC clock output –33MHz nominal O 3.3V The LPC_CLK frequency is 33MHz on this platform Page 33 Copyright © 2021 ADLINK Technology, Inc.
Page 34: Usb
I 3.3VSB PU 10K for this line shall be present on the module. An open 3.3VSB drain driver from a USB current monitor on the carrier board may drive this line low. Page 34 Copyright © 2021 ADLINK Technology, Inc.
Page 35 Not supported USB0_HOST_PRSNT Module USB client may detect the presence of a USB I 3.3VSB host on USB0. A high value indicates that a host is present. Page 35 Copyright © 2021 ADLINK Technology, Inc.
Page 36: Spi Bus (Bios Only)
PU 10K Carrier shall pull to GND or leave not- connected. 3.3VSB BIOS_DIS1# Selection strap to determine the BIOS boot device. PU 10K Carrier shall pull to GND or leave not- connected 3.3VSB Page 36 Copyright © 2021 ADLINK Technology, Inc.
Page 37: Miscellaneous
TPM_PP Trusted Platform Module (TPM) Physical Presence pin. I 3.3V PD 100K Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM. Page 37 Copyright © 2021 ADLINK Technology, Inc.
Page 38: Smbus
General purpose I²C port data I/O line I/O OD PU 2.2K Source SEMA BMC as default (chipset by BOM 3.3VSB 3.3VSB option) Note: I2C default from EC. I2C from SoC is build option support, by project basis. Page 38 Copyright © 2021 ADLINK Technology, Inc.
Page 39: General Purpose I/O (Gpio)
O CMOS Power rail tolerance 5V, 12V 3.3V There shall be PD on carrier board SER1_RX A102 General purpose serial port receiver I CMOS PU 10K 3.3V Power rail tolerance 5V, 12V 3.3V Page 39 Copyright © 2021 ADLINK Technology, Inc.
Page 40: Power And System Management
Trigger for Rapid Shutdown. Must be driven to 5V though a <=50-ohm source RAPID_ I CMOS Not supported impedance for ≥ 20 μs. SHUTDOWN 5VSB Page 40 Copyright © 2021 ADLINK Technology, Inc.
Page 41: Power And Ground
A1, A11, A21, A31, A41, A51, Ground - DC power and signal and AC signal return A57, A60, A66, A70, A80, A90, path. A100, A110, B1, B11, B21, B31, B41, B51, B60, B70, B80, B90, B100, B110 Page 41 Copyright © 2021 ADLINK Technology, Inc.
Page 42: Cd Connector Signal Descriptions
I PCIE AC coupled on module USB_SSRX3+ data path on USB3 USB_SSTX3- Additional Transmit signal differential pairs for the SuperSpeed O PCIE AC coupled on module USB_SSTX3+ USB data path on USB3 Page 42 Copyright © 2021 ADLINK Technology, Inc.
Page 43: Pci Express
AC coupled off Module PCIE_RX7+ PCI Express channel 7, Receive Input differential pair. I PCIE PCIE_RX7- By a PCIe switch, project basis Note: PCIe Lane 6, 7 are supported by PCIe switch, by project basis. Page 43 Copyright © 2021 ADLINK Technology, Inc.
Page 44 GPP 6 PCIE3 GPP 7 PCIE4 GPP 2 PCIE5 GPP 3 PCIE6 BOM option support by project basis through a PCIe switch PCIE7 BOM option support by project basis through a PCIe switch Page 44 Copyright © 2021 ADLINK Technology, Inc.
Page 45: Ddi1 Port
DP_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX_SEL pin function. Page 45 Copyright © 2021 ADLINK Technology, Inc.
Page 46 Management and Device Control 3.3V DDI1_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1M DP mode enabled 1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode Page 46 Copyright © 2021 ADLINK Technology, Inc.
Page 47 I/O OD CMOS DDI1_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1M HDMI mode enabled 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode Page 47 Copyright © 2021 ADLINK Technology, Inc.
Page 48: Ddi2 Port
DP_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX_SEL pin function. Page 48 Copyright © 2021 ADLINK Technology, Inc.
Page 49 Management and Device Control 3.3V DDI2_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1M DP mode enabled 1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode Page 49 Copyright © 2021 ADLINK Technology, Inc.
Page 50 I/O OD CMOS DDI2_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1M HDMI mode enabled 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode Page 50 Copyright © 2021 ADLINK Technology, Inc.
Page 51: Ddi3 Port
DP_AUX+ /- pair must be AC coupled. A set of FET switches is usually used to sort this out. The FET gates can be controlled by the AUX_SEL pin function. Page 51 Copyright © 2021 ADLINK Technology, Inc.
Page 52 Management and Device Control 3.3V DDI3_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1, DP mode enabled 1M pull-down to logic ground enables HDMI Floating enables DisplayPort mode Page 52 Copyright © 2021 ADLINK Technology, Inc.
Page 53 I/O OD CMOS DDI3_DDC_AUX_SEL Strapping Signal to select HDMI or DP output I 3.3V PD 1M HDMI mode enabled 1M pull-down to logic ground enables HDMI Leve this signal floating enables DisplayPort mode Page 53 Copyright © 2021 ADLINK Technology, Inc.
Page 54: Pcie Graphics Port (Peg)
Type 6 PEG_RX4+ PCI Express Graphics receive differential pairs. I PCIE AC coupled off Module PEG_RX4- These are the same lines as PCIE_TX[16:31]+ and – in Module pin- out Type 6 Page 54 Copyright © 2021 ADLINK Technology, Inc.
Page 55 I 3.3V Not supported Carrier Board to reverse lane order. Note: Only lanes 0-7 from the 16 lanes of the PEG port are supported. The available configurations are one x8 or two x4. Page 55 Copyright © 2021 ADLINK Technology, Inc.
Page 56: Module Type Definition
Carrier Board logic may also implement a fault indicator such as an LED. TYPE10# In case of a type 10 module this pin signal is tied to GND through a 47K resistor Not Connected on the module. Page 56 Copyright © 2021 ADLINK Technology, Inc.
Page 57: Power And Ground
C76, C80, C84, C87, C90, C93, C96, C100, C103, C110, D1, D2, D5, D8, D11, D14, D21, D31, D41, D51, D60, D67, D70, D73, D76, D80, D84, D87, D90, D93, D96, D100, D103, D110 Page 57 Copyright © 2021 ADLINK Technology, Inc.
Page 58: Additional Features
The locations of these items is as below: Status Status LEDs LEDs BIOS BIOS 30-pin 30-pin default default debug debug Reset Reset connector connector BIOS BIOS Boot Boot Select Select Figure 3 – Module feature locations Page 58 Copyright © 2021 ADLINK Technology, Inc.
Page 59: Debug Connector
This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module: Test points measurement of internal power rails I2C bus for BIOS POST code readout SPI BIOS programming interface Embedded Controller programming interface Figure 4 – cExpress-AR and Debug Module Page 59 Copyright © 2021 ADLINK Technology, Inc.
Page 60: Status Leds
Rebooted after PWRBTN WD LED = LED OFF Rebooted after RESET BTN WD LED = LED OFF Note: only a RESET not initiated by the BMC can clear the WD LED (user action) Page 60 Copyright © 2021 ADLINK Technology, Inc.
Page 61: Exception Codes
5.3. Exception Codes Exception Code Error Message NOERROR NO_SUSCLK NO_SLP_S5 NO_SLP_S4 NO_SLP_S3 BIOS_FAIL RESET_FAIL RESETIN_FAIL NO_CB_PWROK CRITICAL_TEMP POWER_FAIL VOLTAGE_FAIL RFID_MEMFAIL (No Used) NO_VDDQ_PG NO_V1P05A_PG NO_VCORE_PG NO_SYS_GD NO_V5SBY NO_V3P3A NO_V5_DUAL NO_PWRSRC_GD NO_P_5V_3V3_S0_PG NO_SAME_CHANNEL NO_1V2A_PG Page 61 Copyright © 2021 ADLINK Technology, Inc.
Page 62: Fan Connector
User’s Guide PICMG COM.0 R3.0 5.4. Fan Connector Connector type: JVE 24W1125A-04M00 4 3 2 1 Name Description FAN_PWMOUT FAN_TACHIN Page 62 Copyright © 2021 ADLINK Technology, Inc.
Page 63: Bios Default Reset Button
2. Keep the BIOS Setup Defaults Reset Button pressed and boot up the system. You can release the button when the BIOS prompt screen appears 3. The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system. Page 63 Copyright © 2021 ADLINK Technology, Inc.
Page 64: Bios Boot Select
In either mode, BIOS Select and Mode Configuration Switch Pin 1 is used to select whether to boot from SPI0 or SPI1. Mode Pin 1 Pin 2 Boot from SPI0 (default) Boot from SPI1 Set BIOS to PICMG mode (default) Set BIOS to Failsafe BIOS mode Page 64 Copyright © 2021 ADLINK Technology, Inc.
Page 65: Bios Checkpoints, Beep Codes
These PCI add-on cards show the value of I/O port 80h on an LED display. Aptio V Checkpoint and Beep Codes Download the Aptio V Checkpoint and Beep Codes from the AMI website at: www.ami.com/download/aptio-v-checkpoint-and-beep-codes Page 65 Copyright © 2021 ADLINK Technology, Inc.
Page 66: Software Support
User’s Guide PICMG COM.0 R3.0 7. Software Support 7.1. Operating Systems Windows 10 IOT Enterprise 64-bit • Windows 10 64-bit • Ubuntu 20.04 (planning) • Page 66 Copyright © 2021 ADLINK Technology, Inc.
Page 67: Mechanical And Thermal
All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances on the module connector locating peg holes (dimensions [16.50, 6.00]&[16.50,18.00]) should be ± 0.10mm. Figure 5 – Module mechanical dimensions Page 67 Copyright © 2021 ADLINK Technology, Inc.
Page 70: Heatsink High Profile: Thsh
User’s Guide PICMG COM.0 R3.0 8.2.3 Heatsink High Profile: THSH Dimensions: mm Figure 8 – Heatsink High Profile: THSH Page 70 Copyright © 2021 ADLINK Technology, Inc.

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