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Abov MC80F7708 User Manual

8-bit single-chip microcontrollers
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ABOV SEMICONDUCTOR Co. Ltd.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F7708
User's Manual
(Ver. 1.21)

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Summary of Contents for Abov MC80F7708

  • Page 1 ABOV SEMICONDUCTOR Co. Ltd. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F7708 User’s Manual (Ver. 1.21)
  • Page 2 ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
  • Page 3 14. WATCH DOG TIMER ........62 Difference between auto baud rate and ACK mode ............. 108 15. ANALOG TO DIGITAL CONVERTER ....64 Reference ISP Circuit Diagram and ABOV Sup- 16. BUZZER OUTPUT FUNCTION ......67 plied ISP Board ..........109 17. INTERRUPTS ..........69 A.
  • Page 4 MC80F7708 Terminology List ..........ii Instruction Set ...........iv Instruction Map ..........iii December 3, 2012 Ver 1.21...
  • Page 5 1.1 Description The MC80F7708 are an advanced CMOS 8-bit microcontroller with 8K bytes of FLASH ROM(MTP). This device is one of the MC800 family and a powerful microcontroller which provides a high flexibility and cost effective solution to many LCD applications.
  • Page 6 MC80F7708 • Internal Resistor for LCD Bias • 14 Interrupt sources - External Interrupt : 4 • 42/40 Programmable I/O Pins - Timer : 4 - UART : 2 I/O: 17 - ADC, WDT, WT, BIT I : 1 MC80F7708Q I/O with SEG/COM:24 •...
  • Page 7 MC80F7708 1.3 Development Tools The MC80F7708 are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr. OTP programmers. There are two different type of pro- grammers such as single type and gang type. For mode de- tail, Macro assembler operates under the MS-Windows 95 and upversioned Windows OS.
  • Page 8 MC80F7708 Stand Alone Gang4 USB (Gang Writer) UART ISP B/D Stand Along Gang8 (Gang Writer) December 3, 2012 Ver 1.21...
  • Page 9 MC80F7708 1.4 Ordering Information Device name ROM Size RAM size Package MC80F7708Q 8K bytes FLASH 256 bytes 44MQFP MC80F7708K 8K bytes FLASH 256 bytes 42SDIP - Pb free package; The “P” suffix will be added at original part number. For example; MC80F7708Q(Normal package), MC80F7708Q P(Pb free package)
  • Page 10 MC80F7708 2. BLOCK DIAGRAM Segment Drive Output Common Drive Output SEG0 ~ SEG15 COM0 ~ COM7 (SEG0 ~ SEG19) (COM0 ~ COM3) BIAS Selection circuit LCD Controller/Driver (LCDC) Internal Resistor for LCD Bias Power Supply Accumulator Stack Pointer Circuit Data...
  • Page 11 MC80F7708 3. PIN ASSIGNMENT 44MQFP (Top View) R74 / COM3 R60 / SEG8 R75 / COM2 R57 / SEG7 R76 / COM1 R56 / SEG6 R77 / COM0 R55 / SEG5 R25 / AN5 R54 / SEG4 MC80F7708Q R24 / AN4...
  • Page 12 MC80F7708 4. PACKAGE DIAGRAM 44MQFP 13.45 12.95 10.10 9.90 UNIT: MM 0-7° SEE DETAIL “A” 1.03 0.73 2.35 max. 1.60 Typ. 0.80 Typ. 0.45 0.30 DETAIL “A” 42SDIP UNIT: INCH 1.470 1.450 0.600 Typ. 0.550 0.530 0.070 Typ. 0.045 0.020 0-15°...
  • Page 13 MC80F7708 5. PIN FUNCTION : Supply Voltage. In addition, R1 serves the function of the following special feature. : Circuit ground. RESET: Reset the MCU Reset. Port pin Alternate function : Input to the inverting oscillator amplifier and input to PWM1/T2O the internal main clock operating circuit.
  • Page 14 MC80F7708 units by R5PSR Register. R70~R77: R7 is a 4-bit CMOS input port or LCD segment output. Each pins can be set in digital input or segment out- put mode in 1-bit units by R7PSR Registe Port pin Alternate function...
  • Page 15 MC80F7708 Secondary Pin No. Primary Function State State Function PIN NAME @ Reset @ STOP Description Description MC80F7708Q MC80F7708K Supply Voltage Circuit Ground RESET / R47 Reset (low active) ‘L’ input ‘H’ input /R43, Main clock oscilla- 12,11 Oscillation ‘L’, ‘H’...
  • Page 16 MC80F7708 6. PORT STRUCTURES R01/EC0, R06/INT0, R07/INT1, R41/IN2, R44/INT3 R20/AN0~R23/AN3, R24/AN4~R25/AN5 Pull up Pull-up Tr. Reg. Pull up Pull-up Tr. Reg. Open Drain Reg. Open Drain Reg. Data Reg. Data Reg. Dir. Reg. Dir. Reg. Sub Func. Noise Input Data Canceller Sub Func.
  • Page 17 MC80F7708 (Crystal or Ceramic resonator) R43 (X ), R42 (X MAIN CLOCK Pull-up Pull-up Reg. Open Drain Reg. Data Reg. Direction Reg. / R43 STOP Data Bus (@RC, R) IN8MCLK IN4MCLK IN2MCLK ÷ 4 IN8MCLKXO (‘H’ Output@STOP) IN4MCLKXO IN2MCLKXO CLOCK option...
  • Page 18 MC80F7708 R53/SEG3~R57/SEG7, R60/SEG8~R67/SEG15 R50/SEG0/RX0, R52/SEG2/ACK R70/SEG16/COM7~R70/SEG19/COM4 R74/COM3~R77/COM0 VCL3 or VCL2 or VCL1 VCL3 or VCL2 or VCL1 LCD Data Reg. LCD Data Reg. Frame Counter Frame Counter LCD Control LCD Control VCL0 or V VCL0 or V Reg. Data Reg.
  • Page 19 MC80F7708 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........... -0.3 to +6.0 V Maximum current (ΣI )........60 mA Storage Temperature ........-45 to +125 °C Note: Stresses above those listed under “Absolute Maxi- Voltage on any pin with respect to Ground (V mum Ratings”...
  • Page 20 MC80F7708 7.3 DC Electrical Characteristics = -40~85°C, V =2.2~5.5V, V =0V) Specifications Parameter Symbol Pin / Condition Unit Min. Typ. Max. 0.7V +0.3 R0~R7 Input High Voltage RESET, X , SX , INT0~3, EC0 0.8V +0.3 R0~R7 -0.3 0.3V Input Low Voltage...
  • Page 21 MC80F7708 7.4 LCD Characteristics = -40~85°C, V =2.2~5.5V, V =0V) Specifications Parameter Symbol Condition Unit Min. Typ. Max. LCD Common Output Voltage Deviation=0.2V Output Current μA LCD Segment − Output Voltage Deviation=0.2V Output Current 7.5 A/D Converter Characteristics (TA=25°C, V =3.072V@f...
  • Page 22 MC80F7708 7.6 AC Characteristics (TA=25°C, V =4V, AV =4V, V =0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Main Operating Frequency Sub Operating Frequency 32.768 5000 System Clock Frequency Main Oscillation Stabilization Time (4MHz) Sub Oscillation , SX Stabilization Time...
  • Page 23 MC80F7708 MCPW MCPW 0.9V 0.1V SCPW SCPW 0.9V 0.1V 0.8V INT0 INT1 0.2V RESET 0.2V 0.8V 0.2V Figure 7-1 AC Timing Chart December 3, 2012 Ver 1.21...
  • Page 24 MC80F7708 7.7 Typical Characteristics These graphs and tables are for design guidance only and sents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively are not tested or guaranteed. where σ is standard deviation In some graphs or tables, the data presented are out- side specified operating range (e.g.
  • Page 25 MC80F7708 8. MEMORY ORGANIZATION The have separate address spaces for Program memory, gram memory. Data memory can be read and written to up Data Memory and Display memory. Program memory can to 1024 bytes including the stack area. Display memory only be read, not written to.
  • Page 26 MC80F7708 [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. V G B H RESET VALUE : 00 CARRY FLAG RECEIVES NEGATIVE FLAG...
  • Page 27 MC80F7708 At execution of a At acceptance At execution At execution CALL/TCALL/PCALL of interrupt of RET instruction of RETI instruction 015C 015C 015C 015C 015D 015D 015D 015D Push Push 015E 015E 015E 015E down down 015F 015F 015F 015F...
  • Page 28 MC80F7708 8.2 Program Memory A 16-bit program counter is capable of addressing up to Example: Usage of TCALL 64K bytes, but this device has 8K bytes program memory space only physically implemented. Accessing a location TCALL 0FH ;1BYTE INSTRUCTION above FFFF will cause a wrap-around to 0000 ;INSTEAD OF 2 BYTES...
  • Page 29 MC80F7708 Address Program Memory 0FFC0 TCALL 15 TCALL 14 TCALL 13 Address PCALL Area Memory TCALL 12 0FF00 TCALL 11 TCALL 10 TCALL 9 PCALL Area TCALL 8 (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 0FFFF TCALL 3...
  • Page 30 MC80F7708 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H; Device : MC807708 WT_INT ; Watch Timer / Watch Dog Timer BIT_INT; Basic Interval Timer AD_Con; AD converter NOT_USED; Not Used TMR3_INT ; Timer-3 TMR2_INT; Timer-2 TMR1_INT;...
  • Page 31 User Memory function blocks for controlling the desired operation of the The MC80F7708 have 256 × 8 bits for the user data mem- device. Therefore these registers contain control and status ory (RAM). There are three pages internal RAM. Page is bits for the interrupt system, the timer/counters, analog to selected by G-flag and RAM page selection register RPR.
  • Page 32 MC80F7708 routine at the execution of a subroutine call instruction or the stack pointer (SP). The SP is automatically decreased the acceptance of an interrupt. after the saving, and increased before the restoring. This means the value of the SP indicates the stack location When returning from the processing routine, executing the number for the next save.
  • Page 33 MC80F7708 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00C9H R4 Direction Register R4IO - 0 0 0 0 0 0 - byte 00CAH R5 port data register 0 0 0 0 0 0 0 0...
  • Page 34 MC80F7708 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00EAH Watch Timer Mode Register WTMR R / W 0 0 - - 0 0 0 0 byte, bit 00F4H Interrupt Generation Flag Register High...
  • Page 35 MC80F7708 8.4 Addressing Mode (3) Direct Page Addressing → dp The MC80F7708 use six addressing modes; • Register addressing In this mode, a address is specified within direct page. • Immediate addressing Example; G=0 ;A ←RAM[35 • Direct page addressing C535 •...
  • Page 36 MC80F7708 The operation within data memory (RAM) X indexed direct page, auto increment→ {X}+ ASL, BIT, DEC, INC, LSR, ROL, ROR In this mode, a address is specified within direct page by Example; Addressing accesses the address 0135 regard- the X register and the content of X is increased by 1.
  • Page 37 MC80F7708 Y indexed direct page (8 bit offset) → dp+Y 3F35 This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above. Use Y register instead of X.
  • Page 38 MC80F7708 Y indexed indirect → [dp]+Y Absolute indirect → [!abs] Processes memory data as Data, assigned by the data The program jumps to address specified by 16-bit absolute [dp+1][dp] of 16-bit pair memory paired by Operand in Di- address. rect page plus Y-register data.
  • Page 39 (R0 port direction reg- ister) during initial setting as shown in Figure 9-1. Pull-up control bit All the port direction registers in the MC80F7708 have 0 0: Disconnect 1: Connect written to them by reset function. Therefore, its initial sta- tus is input.
  • Page 40 MC80F7708 9.2 I/O Ports Configuration R0 Port R0 is a 4-bit CMOS bidirectional I/O port (address 0C0 Port Pin Alternate Function Each I/O pin can independently used as an input or an out- put through the R0IO register (address 0C1...
  • Page 41 MC80F7708 nipulation instruction. Do not use read or read-modify-write instruction. Use byte manipulation instruction. ADDRESS : 0C2 R1 Data Register RESET VALUE : -------0 Note: The R24 and R25 are not supported in the MC80F7708K. ADDRESS : 0C3 R1 Direction Register...
  • Page 42 MC80F7708 ADDRESS : 0C8 R4 Data Register RESET VALUE : -000000- Port Pin Alternate Function INT2 (External Interrupt 2) (Oscillation Output) ADDRESS : 0C9 R4 Direction Register RESET VALUE : -000000- (Oscillation Input) R4IO INT3 (External Interrupt 3) (Subsystem Oscillation Input)
  • Page 43 MC80F7708 R6 Ports R7 is multiplexed with LCD common output (COM7 ~ COM0) and segment output(SEG16 ~ SEG19), which can R6 is an 8-bit CMOS bidirectional I/O port (address be selected by writing appropriate value into the ). Each I/O pin can independently used as an input or...
  • Page 44 MC80F7708 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the The internal system clock should be selected to main oscil- basic clock pulses which provide the system clock to be lation by setting bit1 and bit0 of the system clock mode supplied to the CPU and the peripheral hardware.
  • Page 45 MC80F7708 The SCMR should be set to operate by main oscillation. “001” to select main oscillation. Bit2, bit1 and bit0 of the SCMR should be set to “000” or SCMR (System Clock Mode Register) R/W R/W ADDRESS: 0E7 INITIAL VALUE: -----000...
  • Page 46 MC80F7708 11. BASIC INTERVAL TIMER The MC80F7708 have one 8-bit Basic Interval Timer that interrupt to be generated. The Basic Interval Timer is con- is free-run and can not stop. Block diagram is shown in trolled by the clock control register (CKCTLR) shown in Figure 11-1.
  • Page 47 MC80F7708 ADDRESS: 0E6 CKCTLR BCK2 BCK1 BCK0 SELSUB WDTON INITIAL VALUE: --010111 SUB Clock Selection Basic Interval Timer source clock select ÷ 0 : Deselect Sub Clock 000: f MAIN ÷ 1 : Select Sub Clock 001: f MAIN ÷...
  • Page 48 MC80F7708 12. TIMER / COUNTER Timer/Event Counter consists of prescaler, multiplexer, 8- most clock consists of 2048 oscillator periods, the count bit timer data register, 8-bit counter register, mode register, rate is 1/2 to 1/2048 of the oscillator frequency in Timer0.
  • Page 49 MC80F7708 TM0, TM2 (Timer0, 2 Mode Control Register) Bit : ADDRESS: 0D0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE:--000000 Bit : ADDRESS: 0D6 CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST INITIAL VALUE:--000000 CAP0,CAP2 (Capture Mode Selection Bit) T0CK[2:0],T2CK[2:0] (Timer 0,2 Input Clock Selection)
  • Page 50 MC80F7708 T0 (Timer0 Register) Bit : ADDRESS: 0D1 INITIAL VALUE:00H CDR0 (Timer0 Input Capture Register) Bit : ADDRESS: 0D1 CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00 INITIAL VALUE:00H In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.
  • Page 51 MC80F7708 T2 (Timer2 Register) Bit : ADDRESS: 0D7 INITIAL VALUE:00H CDR2 (Timer2 Input Capture Register) Bit : ADDRESS: 0D7 CDR27 CDR26 CDR25 CDR24 CDR23 CDR22 CDR21 CDR20 INITIAL VALUE:00H In Timer mode, this register is the value of Timer 2 counter and in Capture mode, this register is the value of input capture.
  • Page 52 Table 12-1 Operating Modes of Timer 0 and Timer 1 12.1 8-Bit Timer/Counter Mode The MC80F7708 have four 8-bit Timer/Counters, Timer0, 12-1. To use as an 8-bit timer/counter mode, bit CAPx of Timer1, Timer2 and Timer3 as shown in Figure 12-4.
  • Page 53 MC80F7708 Bit : ADDRESS : 0D6 RESET VALUE : --000000 CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST ADDRESS : 0D8 16BIT PWM1E T3CK1 T3CK0 T3CN T3ST RESET VALUE : 000-0000 X : The value “0” or “1” corresponding your operation. T2CK[2:0]...
  • Page 54 MC80F7708 T0,1,2,3 TDR0,TDR1,TDR2,TDR3 TIME Interrupt period x (n+1) Timer 0,1,2,3 (T0IF,T1IF,T2IF,T3IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 12-6 Counting Example of Timer Data Registers T0,1,2,3 TDR0,TDR1,TDR2,TDR3 enable disable clear & start stop TIME Timer 0 (T0IF) Interrupt Occur interrupt...
  • Page 55 MC80F7708 should be set to “1” respectively. Bit : ADDRESS : 0D0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST RESET VALUE : --000000 ADDRESS : 0D2 16BIT T1CK1 T1CK0 T1CN T1ST RESET VALUE : -0--0000 X : The value “0” or “1” corresponding your operation.
  • Page 56 MC80F7708 12.3 8-Bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer flow occurrence. mode register TM0 (bit CAPx of timer mode register TMx Timer/Counter still does the above, but with the added fea- for Timer 1,2,3) as shown in Figure 12-10.
  • Page 57 MC80F7708 Bit : ADDRESS : 0D0 RESET VALUE : --000000 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST ADDRESS : 0D2 16BIT CAP1 T1CK1 T1CK0 T1CN T1ST RESET VALUE : -0--0000 T0CK[2:0] T0ST 0 : Stop Edge Detector 1 : Clear and Start...
  • Page 58 MC80F7708 Bit : ADDRESS : 0D6 RESET VALUE : --000000 CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST ADDRESS : 0D8 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3ST RESET VALUE : 000-0000 T2CK[2:0] T2ST 0 : Stop 1 : Clear and Start...
  • Page 59 MC80F7708 This value is loaded to CDR0(1,2,3) T0,1,2,3 TIME Ext. INT0(1,2,3) Pin 20ns Interrupt Request (INT0F,INT1F) Interrupt Interval Period Ext. INT0 Pin Interrupt Request 20ns (INT0IF) Delay Capture Clear & Start (Timer Stop) Figure 12-12 Input Capture Operation Ext. INT0 Pin...
  • Page 60 MC80F7708 12.4 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except In 16-bit mode, the bits TxCK1,TxCK0 and 16BIT of that the Timer register is running with 16 bits. TM1,TM3 should be set to “1” respectively.
  • Page 61 Figure 12-15 16-bit Capture Mode (Timer2,3) 12.5 8-Bit (16-Bit) Compare Output Mode The MC80F7708 have a function of Timer Compare Out- In addition, 16-bit Compare output mode is available, also. put. To pulse out, the timer match can goes to port pin This pin output the signal having a 50: 50 duty square (R10) as shown in Figure 12-4 and Figure 12-8.
  • Page 62 MC80F7708 duty cycle). If it needed more higher frequency of PWM, it should be reduced resolution. The bit POL1 of TM3 decides the polarity of duty cycle. The duty value can be changed when the PWM outputs. Note: If the duty value and the period value are same, the...
  • Page 63 MC80F7708 MAIN POL=1 POL=0 Duty Cycle [(80 +1) x 200nS = 25.8uS] Period Cycle [(1+3FF ) x 200nS = 204.8uS] T3CK[1:0] = 00 (200nS) T3PPR (8-bit) Period PWM1HR3 PWM1HR2 T3PWHR = 0C T3PPR = FF T3PDR (8-bit) T3PDR = 80...
  • Page 64 MC80F7708 13. WATCH TIMER The watch timer generates interrupt for watch operation. timer is also stopped. If the sub-clock is used as the watch The watch timer consists of the clock selector, 21-bit bina- timer source clock, the watch timer count cannot be ry counter and watch timer mode register.
  • Page 65 MC80F7708 WTCK[2:0] ÷ 2Hz x (7bit WT value + 1) 14 BIT MAIN Timer Counter ÷ (7bit auto reload counter) Binary Counter MAIN WTIN[1:0] MAIN ÷ MAIN WTEN 16 Hz 4 Hz 2 Hz WTIF when f = 32.768 kHz or 7 bit ÷...
  • Page 66 MC80F7708 14. WATCH DOG TIMER The watch dog timer (WDT) function is used for checking ter should be cleared to “0”. program malfunction due to external noise or other causes and return the operation to the normal contion. Note: WDTR and WTR has same address 0E8h. The LOADEN bit is used to select WDTR or WTR.
  • Page 67 MC80F7708 Sour Clock BIT Overflow Binary Counter Counter Clear WDTR[7:0] WDTCL Occur Match WDTIF WDTR <== 1000_0011 Detect Interrupt RESETB RESETB Figure 14-2 Watch Dog Timer Interrupt Time December 3, 2012 Ver 1.21...
  • Page 68 MC80F7708 15. ANALOG TO DIGITAL CONVERTER The analog-to-digital(A/D) converter allows conversion of The processing of conversion is start when the start bit an analog input signal to an corresponding 10-bit digital ADST is set to “1”. After one cycle, it is cleared by hard- value.
  • Page 69 MC80F7708 ADCM (A/D Converter Mode Register) Bit : ADDRESS : 0E2 ADCK ADS3 ADS2 ADS1 ADS0 ADST ADEN RESET VALUE : -0-00001 ADEN (A/D Converter Enable bit) ADS[3:0] (A/D Converter Input Selection) 1 : Enable 0000 : Channel 0 (R20/AN0)
  • Page 70 MC80F7708 fect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor is connected externally as shown below in order to reduce ENABLE A/D CONVERTER noise A/D INPUT CHANNEL SELECT Analog AN0~AN5...
  • Page 71 MC80F7708 16. BUZZER OUTPUT FUNCTION The buzzer driver consists of 6-bit binary counter, the buzzer driving. BUZR[5:0] is initialized to 3F after reset. buzzer driver register BUZR and the clock selector. It gen- Note that BUZR is a write-only register. Frequency calcu- erates square-wave which is very wide range frequency lation is following as shown below.
  • Page 72 MC80F7708 Buzzer Output Frequency When main-frequency is 4MHz, buzzer frequency is shown as below. Frequency Output (kHz) Frequency Output (kHz) BUZR BUZR BUZR[7:6] BUZR[7:6] [5:0] [5:0] 250.000 125.000 62.500 31.250 7.576 3.788 1.894 0.947 125.000 62.500 31.250 15.625 7.353 3.676 1.838...
  • Page 73 MC80F7708 17. INTERRUPTS The MC80F7708 interrupt circuits consist of Interrupt en- Interrupt is generated by ADCIF which is set by finishing able register (IENH, IENM, IENL), Interrupt request flag the analog to digital conversion. register(IRQH, IRQM, IRQL), Interrupt flag register(IN-...
  • Page 74 MC80F7708 Internal bus line I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other Interrupt Enable interrupts are inhibited. When interrupt service is IENH completed by “RETI” instruction, I-flag is set to...
  • Page 75 MC80F7708 IENH (Interrupt Enable High Register) Bit : ADDRESS : 0F6 INT0E INT1E INT2E RX0E TX0E RESET VALUE : -00-00-- IENM (Interrupt Enable Middle Register) Bit : ADDRESS : 0F7 RESET VALUE : 0000---0 IENL (Interrupt Enable Low Register) Bit :...
  • Page 76 MC80F7708 17.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted 2. Interrupt request flag for the interrupt source accepted is or the interrupt latch is cleared to “0” by a reset or an in- cleared to “0”.
  • Page 77 MC80F7708 The following method is used to save/restore the general- General-purpose registers are saved or restored by using purpose registers. push and pop instructions. Example: Register saving INTxx: PUSH ;SAVE ACC. main routine PUSH ;SAVE X REG. acceptance of interrupt...
  • Page 78 MC80F7708 Main Program service TIMER 1 service INT0 service enable INT0 disable other Occur Occur TIMER1 interrupt INT0 enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENM,IENL and master enable "EI"...
  • Page 79 MC80F7708 17.4 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins Figure 17-6 External Interrupt Block Diagram are edge triggered depending on the edge selection register Example: To use as an INT0 IEDS (address 0FC ) as shown in Figure 17-6.
  • Page 80 MC80F7708 18. LCD DRIVER The MC80F7708 has the circuit that directly drives the liq- The MC80F7708 has the segement output port 16 pins uid crystal display (LCD) and its control circuit. The seg- (SEG0 ~ SEG15) and Common output port 8 pins (COM0 ment/common driver directly drives the LCD panel, and ~ COM7).
  • Page 81 MC80F7708 18.1 Control of LCD Driver Circuit The LCD driver is controlled by the LCD Control Register bits of R5PSR, R6PSR or R7PSR to “0”. (LCR). The LCR[1:0] determines the frequency of COM The LCD display can continue to operate during SLEEP signal scanning of each segment output.
  • Page 82 MC80F7708 Note: If the SCKD is set to “1”, the SXIN and SXOUT pin Note: When selecting Sub clock as the LCD clock source, is used as normal I/O pin R45, R46. the WTCK[2:0] bit of WTMR(Watch Timer Mode Register) should be set to “000”...
  • Page 83 MC80F7708 18.2 LCD BIAS Control The MC80F7708 has internal Bias Circuit for driving LCD Note: The self bias check reference can be applied to con- panel. It alse has the contrast controller of 16 step. trast adjustment with VDD voltage variation. Because the...
  • Page 84 MC80F7708 18.3 LCD Display Memory Display data are stored to the display data area (page 4) in the data memory. The display datas which stored to the display data area (ad- dress 0460 -0473 ) are read automatically and sent to the...
  • Page 85 MC80F7708 18.4 Control Method of LCD Driver Initial Setting Flow chart of initial setting is shown in Figure 18-5. Example: Driving of LCD = 32.768kHz) Select Frame Frequency LCR,#4DH =64Hz, 1/4 duty RPR,#4;Select LCD Memory(4 page) SETG #60H Clear C_LCD1: LDA #0 ;RAM Clear...
  • Page 86 MC80F7708 CLRG LDX#<DISPRAM;Address included the data ;to be displayed. GOLCD: LDA{X} Write into the LDA!FONT+Y ;LOAD FONT DATA LDMRPR,#4;Set RPR = 4 to access LCD LCD Memory SETG ;Set Page 4 LDX#60H STA{X}+;LOWER 4 BITS OF ACC. seg0 STA{X} ;UPPER 4 BITS OF ACC. seg1 CLRG ;Set Page = 0...
  • Page 87 MC80F7708 18.5 Duty and Bias Selection of LCD Driver 4 kinds of driving methods can be selected by LCDD[1:0] (bits 3 nally. Figure 18-8 shows typical driving waveforms for LCD.). and 2 of LCD control register) and connection of BIAS pin exter-...
  • Page 88 MC80F7708 19. UNIVERSAL ASYNCHRONOUS SERIAL INTERFACE The Asynchronous serial interface(UART) enables full-duplex The UART driver consists of TXSR0, RXBR0, ASIMR0 and operation wherein one byte of data after the start bit is transmitted BRGCR0 register. Clock asynchronous serial I/O mode (UART) and received.
  • Page 89 MC80F7708 RECEIVE ÷ ÷ ÷ 5-bit counter ÷ ÷ ÷ 1 / 2 match ÷ TX_CLK (Divider) Decoder match 1 / 2 BRGCR RX_CLK (Divider) TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 5-bit counter SEND Data Bus Figure 19-2 Baud Rate Generator Block Diagram 19.1 Asynchronous Serial Interface Configuration...
  • Page 90 MC80F7708 ADDRESS: 0B8 ASIMR0 BTCL PS01 PS00 TX0M RX0M ISRM0 INITIAL VALUE: 0000 -00- Receive Completion Interrrupt Control When Error Occurs 0: Receive completion interrupt request is issued TX0M RX0M (Operation mode) when an error occured 00: Operation stop 1: Receive completion interrupt request is not issued...
  • Page 91 MC80F7708 ADDRESS: 0BA BRGCR0 BTCL TPS1 TPS0 MDL3 MDL2 TPS2 MDL1 MDL0 INITIAL VALUE: -001 0000 Input clock Selection for Baud Rate Generator (k) ÷ ÷ 0000: f 16 (k=0) 1000: f 24 (k=8) ÷ ÷ 0001: f 17 (k=1)
  • Page 92 MC80F7708 19.2 Relationship between main clock and baud rate The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. Transmit/Receive clock generation for baud rate is made by using main system...
  • Page 93 MC80F7708 20. OPERATION MODE The system clock controller starts or stops the main fre- the peripheral hardwares are operated on the high-frequen- quency clock oscillator, which is controlled by system cy clock. At reset release, this mode is invoked. clock mode register (SCMR). Figure 20-1 shows the oper- SLEEP mode ating mode transition diagram.
  • Page 94 MC80F7708 21. POWER DOWN OPERATION MC80F7708 have 2 power down mode. In power down Sleep mode is entered by writing “0F ” into Stop and mode, power consumption is reduced considerably in Bat- Sleep Control Register(SSCR), and STOP mode is entered tery operation that Battery life can be extended a lot.
  • Page 95 MC80F7708 Oscillator Internal CPU Clock RESET Release Set bit 0 of SMR BIT Counter Clear & Start Normal Operation Stand-by Mode = 62.5ms Normal Operation at 4.19MHz by hardware x 256 ÷1024 MAIN Figure 21-3 SLEEP Mode Release Timing by RESET pin 21.2 STOP Mode...
  • Page 96 MC80F7708 Operating Main Main Stop Mode Clock source Operating Mode Sleep Mode Main Clock Oscillation Oscillation Stop Sub Clock Oscillation Oscillation Oscillation System Clock Active Stop Stop Peri. Clock Active Active Stop 1. Except watch timer(sub clock) and LCD driver(sub clock)
  • Page 97 MC80F7708 Oscillator pin) Internal Clock RESET STOP Instruction Executed BIT Counter n+1 n+2 Clear Stop Operation Normal Operation Normal Operation > 62.5ms at 4.19MHz by hardware x 256 ÷1024 MAIN Figure 21-5 STOP Mode Release Timing by RESET December 3, 2012 Ver 1.21...
  • Page 98 MC80F7708 Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user First consider the setting to input mode. Be sure that there...
  • Page 99 MC80F7708 22. OSCILLATOR CIRCUIT The MC80F7708 have three oscillation circuits internally. respectively, inverting amplifier which can be configured and X are input and output for main frequency and for being used as an on-chip oscillator, as shown in Figure and SX are input and output for sub frequency, 22-1.
  • Page 100 MC80F7708 23. RESET The MC80F7708 have has four reset generation sources; (BIR) and watch-dog timer reset. Table 23-1 shows on- external reset input, power on reset (POR), built in reset chip hardware initialization by reset action. On-chip Hardware Initial Value...
  • Page 101 MC80F7708 System Clock RESET ADDRESS FFFE FFFF Start DATA MAIN PROGRAM RESET Process Step Stabilization Time = 65.5mS at 4MHz x 256 ÷1024 MAIN Figure 23-3 Timing Diagram of RESET 23.2 Power On Reset The on-chip POR circuit holds down the device in RESET parmeters (voltage, frequency, temperature...etc) must be...
  • Page 102 MC80F7708 24. Butil In Reset (BIR) The MC80F7708 has an on-chip BIR(Built In Reset) cir- cuitry. The Block diagram of BIR is shown in the Figure cuitry to immunize against power noise. The BIR control 24-1. register BIRR can enable or disable the built in reset cir-...
  • Page 103 MC80F7708 The BIR of MC80F7708 has 8 detection level which can 2.4V, BIR level 2V and 2.4V can not operate. be selected by BIS[2:0] and each level can be trimmed by TRM[1:0]. The NC_SEL bit of BIRR is used for selecting BIR noise RESET VECTOR canceller.
  • Page 104 “ONP” bit of the Device configuration area (20FF ) for when the X is shorted or opened, the main the MC80F7708. oscillation is stopped except by stop instruction and the low frequency noise is entered. The ONP function is like below.
  • Page 105 “OFP” bit of the Device Configuration Area in ONP block as system clock. There is no need to connect (MASK option for MC80F7708). the x-tal, resonator, RC and R externally. After selecting And this function can recover the external clock source the this option, the period of internal oscillator clock could when the external clock is recovered to normal state.
  • Page 106 Figure 26-1 The FLASH Configuration Byte 26.2 FLASH Programming How to Program To program the FLASH or MTP devices, user can use ABOV The MC80F7708 is a MTP microcontroller. Its internal user own programmer. memory is constructed with FLASH ROM..
  • Page 107 3. Set the programming address range as below table. all of ABOV FLASH/OTP devices, also the StandAlone-Gang4 can program four FLASH/OTPs at once for ABOV device. Ask to ABOV sales part for purchasing or more detail. Address Set Value E000...
  • Page 108 CHOICE-Dr. EVA80F77 B/D Rev1.0 S/N_________ 32.768kHz E_VCC T_VCC RESET T_RST (Only Pin) RESET RESET /R47 XOUT (Only Pin) T_XOUT XOUT XOUT /R42 SXin SXIN /R45 SXOUT SXOUT /R46 USER * J_USEC_C is reserved for further use, Unused in MC80F7708. December 3, 2012 Ver 1.21...
  • Page 109 5. Power on a target system. expense in components and circuit board area. The follow- ing section details the procedure for accomplishing the in- 6. Run the ABOV ISP software. stallation procedure. Download the ISP S/W from www.abov.co.kr. Unzip the download file and run ISP_800.exe 1.
  • Page 110 MC80F7708 28.2 Basic ISP S/W Information The Figure 28-1 is the ISP software based on Windows Table 28-2. In case of not detecting its baudrates an user This software is only supporting devices with UART. manually have to select specific baudrates.
  • Page 111 The pull down resistor is for blocking this undefined state. Do not power on a application B/D in ISP mode without connecting a ISP board. 4. Refer to the section 29.4 explaining the auto baudrate. Auto baudrate mode is not supported at MC80F7708 December 3, 2012 Ver 1.21...
  • Page 112 The ISP S/W detects user system clock and MCU configure a Auto Baud Rate baud rate automatically. This mode does not need to connect the ACK mode mode ACK pin of target MCU to ISP B/D. But the MC80F7708 does not support this mode. MC80F0204 MC80F0224 ACK mode...
  • Page 113 MC80F7708 28.6 Reference ISP Circuit Diagram and ABOV Supplied ISP Board The ISP software and hardware circuit diagram are provid- To get a ISP B/D, contact to sales department. The follow- ed at www.abov.co.kr. ing circuit diagram is for reference use.
  • Page 114 MC80F7708 December 3, 2012 Ver 1.21...
  • Page 115 MC80F7708 APPENDIX December 3, 2012 Ver 1.21...
  • Page 116 MC80F7708 A. INSTRUCTION A.1 Terminology List Terminology Description Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit...
  • Page 117 MC80F7708 A.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC “ “ “ #imm...
  • Page 118 MC80F7708 A.3 Instruction Set Arithmetic / Logic Operation BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE ADC #imm ADC dp ADC dp + X ADC !abs Add with carry. NV--H-ZC A ← ( A ) + ( M ) + C...
  • Page 119 MC80F7708 BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC EOR #imm EOR dp EOR dp + X EOR !abs Exclusive OR N-----Z- EOR !abs + Y A ← ( A ) ⊕ ( M ) EOR [ dp + X ]...
  • Page 120 MC80F7708 Register / Memory Operation BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC LDA #imm LDA dp LDA dp + X LDA !abs Load accumulator LDA !abs + Y A ← ( M ) N-----Z- LDA [ dp + X ]...
  • Page 121 MC80F7708 16-BIT Operation BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE 16-Bits add without carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) (YA) − Compare YA contents with memory pair contents :...
  • Page 122 MC80F7708 Branch / Jump Operation BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel Branch if bit set : -------- if ( bit ) = 1 , then pc ←...
  • Page 123 MC80F7708 Control Operation & Etc. BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...