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Abov MC96F1206 User Manual

Cmos single-chip 8-bit mcu with 12-bit adc and ldo
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Introduction
This user's manual targets application developers who use MC96F1206 for their specific needs. It
provides complete information of how to use MC96F1206 device. Standard functions and blocks
including corresponding register information of MC96F1206.
MC96F1206 incorporates followings to offer highly flexible and cost effective solutions: 6Kbytes of
FLASH, 256bytes of IRAM, general purpose I/O, basic interval timer,watchdog timer, 16-bit
timer/counter, 16-bit PWM output, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and
clock circuitry. We introduces rich features such as excellent noise immunity, code optimization,
costeffectiveness, and so on.
Reference documents
MC96F1206 programming tools and manuals released by ABOV: They are available at ABOV
website,
www.abovsemi.com
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:

Figure 1. MC96F1206 Block Diagram

https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator, ABOV Semiconductor
www.abovsemi.com
MC96F1206
User's Manual
CMOS single-chip 8-bit MCU
with 12-bit ADC and LDO
Version 1.22

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Summary of Contents for Abov MC96F1206

  • Page 1: Figure 1. Mc96F1206 Block Diagram

    12-bit ADC and LDO Version 1.22 Introduction This user’s manual targets application developers who use MC96F1206 for their specific needs. It provides complete information of how to use MC96F1206 device. Standard functions and blocks including corresponding register information of MC96F1206.

  • Page 2: Table Of Contents

    Contents MC96F1206 User’s manual Contents Device overview ....................... 8 Block diagram ........................ 10 Pinouts ........................... 11 Pin description ........................ 13 GPIO port structure ......................15 External interrupt I/O port structure ................16 Program memory ......................17 Internal data memory ..................... 18 Extended SFR area......................
  • Page 3 MC96F1206 User’s manual Contents 6.12.1 Interrupt Enable registers (IE, IE1) ................. 46 6.12.2 Interrupt Priority registers (IP, IP1) ................. 46 6.12.3 External Interrupt Flag register (EIFLAG) .............. 46 6.12.4 External Interrupt Polarity registers (EIPOL0, EIPOL1) ......... 47 6.12.5 Register map ......................47 6.12.6...
  • Page 4 Contents MC96F1206 User’s manual Serial In-System Program (ISP) mode................93 14.4.1 Flash operation ....................... 93 14.4.2 Flash Read ......................95 14.4.3 Enable program mode .................... 95 14.4.4 Flash write mode ....................95 14.4.5 Flash page erase mode ..................96 14.4.6 Flash bulk erase mode ...................
  • Page 5 MC96F1206 User’s manual List of figures List of figures Figure 1. MC96F1206 Block Diagram ..................... 1 Figure 2. MC96F1206 Block Diagram ....................10 Figure 3. MC96F1206AEN 16 SOPN Pinouts ..................11 Figure 4. MC96F1206 20TSSOP assignment ..................12 Figure 5. MC96F1206 16SOPN assignment ..................12 Figure 6.
  • Page 6 Figure 79. 20 TSSOP Package Outline ....................118 Figure 80. 16SOPN Package Outline ....................119 Figure 81. MC96F1206 Device Numbering Nomenclature ..............120 Figure 82. Flash Protection against Abnormal Operations ..............128 Figure 83. Flowchart of Flash Protection .................... 130...
  • Page 7 MC96F1206 User’s manual List of tables List of tables Table 1. MC96F1206 Device Features and Peripheral Counts .............. 8 Table 2. 16 SOPN Pin Description ......................13 Table 3. SFR Map Summary ......................... 21 Table 4. SFR Map ..........................21 Table 5.

  • Page 8: Device Overview

    MC96F1206 User’s manual Description The MC96F1206 is an advanced CMOS 8-bit microcontroller with 6 Kbytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost-effective solution to many embedded control applications. This provides the following features : 6 Kbytes of FLASH, 256 bytes of SRAM, 16-bit timer/counter/PWM, Watchdog timer with WDTOSC, 12-bit ADC with LDO, On-chip POR, LVI and LVR, Internal RC-Oscillator, Internal WDT-Oscillator and clock circuitry.
  • Page 9 MC96F1206 User’s manual 1. Description Device MC96F1206 Peripheral Interrupt sources  External interrupts: EINT0/1 (2)  PCI1 (1)  Timer : T0/ T1 (2)  WDT (1)  BIT (1)  ADC (1) LVI (1)  Internal RC oscillator 32MHz  2.0% (T ...

  • Page 10: Block Diagram

    1. Description MC96F1206 User’s manual Block diagram Figure 2 describes MC96F1206 in a block diagram. Flash IRAM CORE 256B M8051 On-chip debug In-system programming General purpose I/O 18 ports normal I/O Power control Power on reset Low voltage reset Watchdog timer...

  • Page 11: Pinouts And Pin Descriptions

    MC96F1206 User’s manual 2. Pinouts and pin descriptions Pinouts and pin descriptions In this chapter, MC96F1206 pinouts and pin descriptions are introduced. Pinouts RESETB/INT0/P02 P20/AN13 AN2/P03 P17/AN12 MC96F1206US P16/AN11 AN3/P04 (20QFN) AN4/P05 P15/AN10 P14/AN9 AN5/P06 Figure 3. MC96F1206AEN 16 SOPN Pinouts...

  • Page 12: Figure 4. Mc96F1206 20Tssop Assignment

    DSDA/EC0/AN0/P00 P20/AN13 DSCL/AN1/P01 RESETB/INT0/P02 P17/AN12 AN2/P03 MC96F1206R P16/AN11 (20TSSOP) AN3/P04 P15/AN10 AN4/P05 P14/AN9 AN5/P06 P13/AN8/INT1/EC1 AN6/P07 AN7/P10 Figure 4. MC96F1206 20TSSOP assignment P21/AN14 DSDA/EC0/AN0/P00 P20/AN13 DSCL/AN1/P01 MC96F1206M P17/AN12 RESETB/INT0/P02 (16SOPN) AN2/P03 P16/AN11 AN3/P04 P15/AN10 AN4/P05 P14/AN9 AN5/P06 P13/AN8/INT1/EC1 Figure 5. MC96F1206 16SOPN assignment...

  • Page 13: Pin Description

    MC96F1206 User’s manual 2. Pinouts and pin descriptions Pin description Table 2. 16 SOPN Pin Description Pin name Function @reset Shared with Port P0 Input AN0/ EC0/ DSDA 8-bit I/O Port AN1/ DSCL Can be set in input or output...
  • Page 14 2. Pinouts and pin descriptions MC96F1206 User’s manual Pin name Function @reset Shared with EINT0 External interrupt input and Timer P02/RESETB 0 capture input EINT1 External interrupt input and Timer P13/AN8/EC1 1 capture input Input PWM0O Timer 0 pulse output...

  • Page 15: Gpio Port Structure

    MC96F1206 User’s manual 3. Port structures Port structures GPIO port structure Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...

  • Page 16: External Interrupt I/O Port Structure

    3. Port structures MC96F1206 User’s manual External interrupt I/O port structure Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG.

  • Page 17: Memory Organization

    Internal data memory (iRAM) is 256 bytes and it includes the stack area. Program memory A 16-bit program counter is capable of addressing up to 64 Kbytes, but MC96F1206 has only 6 Kbytes program memory space. After reset, CPU begins execution from location 0000H. Each interrupt is assigned to a fixed location of the program memory.

  • Page 18: Internal Data Memory

    4. Memory organization MC96F1206 User’s manual 17FFH 007 FH 006 0H Program Memory Areas 6Kbytes 005 FH 004 0H 003 FH 002 0H 001 FH 000 0H 000 0H Figure 8. Program Memory More detailed description of program memory is introduced in chapter 14.

  • Page 19: Figure 9. Internal Data Memory Map

    MC96F1206 User’s manual 4. Memory organization Figure 9. Internal Data Memory Map The lower 128 bytes of RAM are present in all 8051 devices as mapped in figure 8. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7.

  • Page 20: Extended Sfr Area

    Extended SFR area Extended SFR area has no relation with RAM nor FLASH. This area can be read or written to by using SFR in 8-bit unit but XSFR is not used in MC96F1206. SFR map In this section, information of SFR map and map summaries are introduced through tables 3 to 6.

  • Page 21: Sfr Map Summary

    MC96F1206 User’s manual 4. Memory organization SFR map summary 4.4.1 Table 3. SFR Map Summary – Reserved M8051 compatible NOTE 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H 0F0H FEARL FEARM FEARH 0E8H FEMR FECR FESR FETCR 0E0H P2PU...
  • Page 22 4. Memory organization MC96F1206 User’s manual Watch Dog Timer Mode Register WDTMR – – – – Watch Dog Timer Register WDTR Watch Timer Counter WDTCR Register: Read Case LVI Control Register LVIR P2 Data Register P1 Direction Register P1IO Reserved...
  • Page 23 MC96F1206 User’s manual 4. Memory organization Case Timer 0 Register High, Read Case Capture 0 Data High Register, CDR0H Read Case PWM 0 Period Register Low, Write PWM0PR Case Timer 0 Data Register Low, Write T0DRL Case PWM 0 Period Register Low, Write...
  • Page 24 4. Memory organization MC96F1206 User’s manual Program Status Word Register P0 Pull-up Resistor Selection P0PU Register Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – –...
  • Page 25 MC96F1206 User’s manual 4. Memory organization @ Reset Address Function Symbol Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – –...

  • Page 26: 8051 Compiler Compatible Sfr Map

    4. Memory organization MC96F1206 User’s manual 8051 Compiler Compatible SFR map 4.4.3 ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 27 MC96F1206 User’s manual 4. Memory organization DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 28: I/O Ports

    Ports I/O ports MC96F1206 has two groups of I/O ports, P0 and P1. Each port can be easily configured as an input pin, an output, or an internal pull up and open-drain pin by software. The port configuration pursues to meet various system configurations and design requirements.

  • Page 29: Pin Change Interrupt Enable Register (Pci)

    MC96F1206 User’s manual 5. Ports Pin Change Interrupt Enable Register (PCI) 5.2.6 The P1 can support Pin Change Interrupt function. Pin Change Interrupts PCI will trigger if any enabled P1[7:0] pin toggles. The PCI Register control which pins contribute to the pin change interrupts.

  • Page 30: Register Description Of P0

    5. Ports MC96F1206 User’s manual Register description of P0 5.3.2 P0 (P0 Data Register): 80H Initial value: 00H P0[7:0] I/O Data P0IO (P0 Direction Register): 89H P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO Initial value: 00H P0IO[7:0] P0 Data I/O Direction.

  • Page 31: Port P1

    MC96F1206 User’s manual 5. Ports Port P1 Port description of P1 5.4.1 As a 6-bit I/O port, P1 controls the following registers:  P1 data register (P1)  P1 direction register (P1IO)  P1 pull-up resistor selection register (P1PU) ...

  • Page 32: Port P2

    5. Ports MC96F1206 User’s manual Port P2 Port description of P2 5.5.1 As a 6-bit I/O port, P2 controls the following registers:  P2 data register (P2)  P2 direction register (P2IO)  P2 pull-up resistor selection register (P2PU) ...
  • Page 33 MC96F1206 User’s manual 5. Ports Initial value: 00H PSR01 P13 Port Debounce Enable Register disable enable (about 500us fix) PSR00 P02 Port Debounce Enable Register disable enable (about 500us fix) NOTE) Before you use MCU STOP1/2 mode, you must disable P02, P13 debounce.
  • Page 34 5. Ports MC96F1206 User’s manual AN12 PSR33 P16 Port Selection Register AN11 PSR32 P15 Port Selection Register AN10 PSR31 P14 Port Selection Register PSR30 P13 Port Selection Register PSRPWM (PWM Port Selection Register) : DEH PSRPWM6 PSRPWM5 PSRPWM4 PSRPWM2 PSRPWM1...

  • Page 35: Interrupt Controller

    6. Interrupt controller Interrupt controller Up to 16 interrupt sources are available in the MC96F1206. Allowing software control, each interrupt source can be enabled by defining separate enable register bit associated with it. It can also have four levels of priority assigned. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt sources, and is not controllable by software.

  • Page 36: External Interrupt

    6. Interrupt controller MC96F1206 User’s manual Figure 11. Interrupt Group Priority Level Figure 13 introduces interrupt groups and their priority levels that is available for sharing interrupt priority. Priority of a group is set by 2 bits of Interrupt Priority (IP) registers: 1 bit from IP and another 1 bit from IP1.

  • Page 37: Figure 12. External Interrupt Description

    MC96F1206 User’s manual 6. Interrupt controller Figure 12. External Interrupt Description Figure 13. PCI Interrupt Description...

  • Page 38: Interrupt Controller Block Diagram

    6. Interrupt controller MC96F1206 User’s manual Interrupt controller block diagram Priority EIEDGE[A5 EIPOLA[A6 IE[A8 IP[B8 IP1[F8 EIBOTH[A7 Priority High FLAG0 INT0 FLAG1 INT1 FLAG2 PCI1 reserved reserved Release Stop/Sleep EXTRG IE1[A9 reserved TMIF0 TMIF1 EA(IE.7[A8 LVIRF BITF WDTIFR Priority Low Figure 14.

  • Page 39: Interrupt Sequence

    MC96F1206 User’s manual 6. Interrupt controller Table 6. Interrupt Vector Address Table Interrupt source Symbol Interrupt Priority Mask Vector Enable Bit address Hardware Reset RESETB Non-Maskable 0000H External Interrupt 0 INT0 IE.0 Maskable 0003H External Interrupt 1 INT1 IE.1 Maskable...

  • Page 40: Table 7. Ljmp Description And Example Code

    6. Interrupt controller MC96F1206 User’s manual Table 7. LJMP Description and Example Code Instruction LJMP Example code LJMP 4000H NOTE: After finishing LJMP, NOP located at the address 400H will be executed as the next instruction.

  • Page 41: Figure 15. Interrupt Sequence Flow

    MC96F1206 User’s manual 6. Interrupt controller Figure 15 shows a flow diagram of an ISR process. Figure 15. Interrupt Sequence Flow...

  • Page 42: Effective Timing After Controlling Interrupt Bit

    6. Interrupt controller MC96F1206 User’s manual Effective timing after controlling interrupt bit Case A in figure 16 shows an effective time of Control Interrupt Enable Register (IE, IE1). Figure 16. Case A: Effective Timing of Interrupt Enable Register Case B in figure 17 shows an effective time of Interrupt Flag Register.

  • Page 43: Interrupt Enable Accept Timing

    MC96F1206 User’s manual 6. Interrupt controller Figure 18. Effective Timing of Multi Interrupt Figure 17 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred. Then INT0 is served immediately, then remain part of INT1 service routine is executed.

  • Page 44: Interrupt Service Routine Address

    6. Interrupt controller MC96F1206 User’s manual Figure 19. Interrupt Response Timing Diagram Interrupt Service Routine Address As seen in figure 20, ISR can be placed at any other location in program memory, and program memory must provide an unconditional jump to the starting address of ISR from the corresponding vector address.

  • Page 45: Interrupt Timing

    MC96F1206 User’s manual 6. Interrupt controller Figure 21. Saving and Restore Process Diagram and Example Code Example code in figure 21 performs the followings: Interrupt INTXX occurs. PUSH PSW: the SP is incremented by one, and the value of the specified byte operand is stored at the internal RAM address indirectly referenced by the SP.

  • Page 46: Interrupt Register

    6. Interrupt controller MC96F1206 User’s manual NOTES Command cycle CLPx imply the followings: L ➔ Last cycle 1 ➔ 1 cycle or 1 phase 2 ➔ 2 cycle or 2 phase Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt register Interrupt registers are memory space used to control interrupt functions.

  • Page 47: External Interrupt Polarity Registers (Eipol0, Eipol1)

    MC96F1206 User’s manual 6. Interrupt controller The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing ‘0’ to it. 6.12.4 External Interrupt Polarity registers (EIPOL0, EIPOL1) External interrupt polarity 0 register (EIPOL0) and external interrupt polarity 1 register (EIPOL1) determine one from rising edge, falling edge, and both edges for interrupt.
  • Page 48 6. Interrupt controller MC96F1206 User’s manual IE (Interrupt Enable Register): A8H INT5E INT2E INT1E INT0E Initial value: 00H Enable or disable all interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or disable ADC Interrupt ADC interrupt Disable ADC interrupt Enable...
  • Page 49 MC96F1206 User’s manual 6. Interrupt controller IP (Interrupt Priority Register): B8H – – – – Initial value: 00H IP1 (Interrupt Priority Register 1): F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP[5:0], IP1[5:0] Select Interrupt Group Priority...
  • Page 50 6. Interrupt controller MC96F1206 User’s manual –- – – – – – FLAG1 FLAG0 – – – – – – Initial value : 0H EDGE1 Determines the type of External interrupt 1, edge or level sensitive. Level (default) Edge EDGE0 Determines the type of External interrupt 0, edge or level sensitive.

  • Page 51: Block Diagram

    MC96F1206 User’s manual 7. Clock generator Clock generator The clock generator produces the basic clock pulses which provide the system clock to CPU and peripheral hardware. The internal RC-OSC is used as system clock and the default division rate is two.
  • Page 52 7. Clock generator MC96F1206 User’s manual SCCR (System and Clock Control Register): 8AH STOP1 DIV1 DIV0 CBYS ISTOP Initial value: 20H STOP1 Control the STOP Mode NOTE) When PCON=0x03, This bit is applied. When PCON=0x01, This bit is not applied.

  • Page 53: Block Diagram

    8. Basic interval timer Basic interval timer The MC96F1206 has one 8-bit Basic Interval Timer that is free-run and can’t stop. Block diagram is shown in . In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITF).

  • Page 54: Table 11. Bit Period Table

    8. Basic interval timer MC96F1206 User’s manual BCCR (BIT Clock Control Register) : 8BH BITF IRC_SEL BCLR BCK2 BCK1 BCK0 Initial value : 06H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ BITF to this bit.

  • Page 55: Block Diagram

    MC96F1206 User’s manual 9. Watchdog timer Watchdog timer The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or an interrupt request.

  • Page 56: Register Map

    9. Watchdog timer MC96F1206 User’s manual WDT Clock Sourece WDT_CNT WDT_CLR occur counter clear WDTR WDTR  0000_0011b Match Detect WDT_flag WDT_RESETB RESET Figure 26. Watchdog Timer Interrupt Timing Waveform Register map Name Address Direction Default Description WDTR Watch Dog Timer Register...
  • Page 57 MC96F1206 User’s manual 9. Watchdog timer WDTMR (Watch Dog Timer Mode Register) : 8DH WDTEN WDTRSON WDTCL WDTIFR Initial value : 00H WDTEN Control WDT operation disable enable WDTRSON Control WDT Reset operation Free Running 8-bit timer Watch Dog Timer Reset ON...

  • Page 58: 16-Bit Timer/ Counter Mode

    10. Timer MC96F1206 User’s manual TIMER The 16-bit timer x(0~1) consists of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, Timer Mode Control Register, PWM Duty High/Low, PWM Period High/Low Register. It is able to use internal 16-bit timer/ counter without a port output function. The 16-bit timer x can be clocked by internal or external clock source (EC0, EC1).

  • Page 59: 16-Bit Capture Mode

    MC96F1206 User’s manual 10. Timer Figure 27. 16-bit Timer/ Counter Mode of TIMER 0/1 Figure 28. 16-bit Timer/ Counter 0/1 Interrupt Example 16-bit capture mode The timer x(0~1) capture mode is set by CAPx as ‘1’ in TxCR register. The clock is same source as Output Compare mode.

  • Page 60: Figure 29. 16-Bit Capture Mode Of Timer 0/1

    10. Timer MC96F1206 User’s manual The CDRxH, PWMxDRH and TxH are in same address. In the capture mode, reading operation is read the CDRxH, not TxH because path is opened to the CDRxH. PWMxDRH will be changed in writing operation. The PWMxDRL, TxL, CDRxL has the same function.

  • Page 61: Figure 30. Input Capture Mode Operation Of Timer 0/1

    MC96F1206 User’s manual 10. Timer Figure 30. Input Capture Mode Operation of TIMER 0/1 Figure 31. Express Timer Overflow in Capture Mode...

  • Page 62: Pwm Mode

    10. Timer MC96F1206 User’s manual PWM Mode The timer x(0~1) has a PWM (pulse Width Modulation) function. In PWM mode, the Tx/PWMx output pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set TX_PE to ‘1’.

  • Page 63: Timer Data And Period/Duty Write

    MC96F1206 User’s manual 10. Timer Figure 33. Example of PWM at 8MHz Figure 34. Example of PWM at 8MHz(Duty=Period) Timer Data and Period/Duty Write When writing a value to the Timer x data registers, write to the TxDRH first, then write to the TxDRL.

  • Page 64: Register Map

    10. Timer MC96F1206 User’s manual TxDRH write TxDRH_BUF TxDRL write Data High Register Data Low Register Timer x start TxDRH TxDRL Compare TxH/L (16-bit Counter)  Figure 35. Timer x Compare Data Write Register map Table 13. TIMER 0 Register Map...

  • Page 65: Register Description For Timer/Counter X

    MC96F1206 User’s manual 10. Timer Register description for Timer/Counter x TxCR (Timer 0~1 Mode Control Register): B2H, BAH TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST Initial value : 00 TxEN Control Timer x Timer x disable Timer x enable...
  • Page 66 10. Timer MC96F1206 User’s manual TxCR1 (Timer 0~1 Mode Control Register 1) : B3H, BBH T32M TxIN[2] TxIN[1] TxIN[0] ECEN Tx_PE Initial value : 00 T32M Select the Timer Clock Source to 32MHz IRC. (Timer0 Only) Clock Source is selected by TxCK[2:0]...
  • Page 67 MC96F1206 User’s manual 10. Timer TxH (Timer 0~1 Register High, Read Case) : B5H, BDH TxH7 TxH6 TxH5 TxH4 TxH3 TxH2 TxH1 TxH0 Initial value : 00 TxH[7:0] TxH Counter Period High data. CDRxH (Capture 0~1 Data High Register, Read Case) : B5H, BDH...
  • Page 68 10. Timer MC96F1206 User’s manual PWMxPRH (PWM 0~1 Period Register High, Write Case) : B7H, BFH PWMxPRH7 PWMxPRH6 PWMxPRH5 PWMxPRH4 PWMxPRH3 PWMxPRH2 PWMxPRH1 PWMxPRH0 R / W Initial value : FF PWMxPRH[7:0] TxPWM Period High data NOTE) Writing is effective only when PWMxE = 1 and TxST = 0...

  • Page 69: Bit A/D Converter

    MC96F1206 User’s manual 11. 12-bit A/D Converter 12-bit A/D Converter The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 12-bit digital value. The A/D module has tenth analog inputs. The output of the multiplex is the input into the converter, which generates the result via successive approximation.

  • Page 70: Block Diagram

    11. 12-bit A/D Converter MC96F1206 User’s manual Block diagram NOTE) BMR : Beta-Multiplier Reference Figure 36. ADC Block Diagram AN0 ~ AN14 Analog Input 0~1000pF Figure 37. A/D Analog Input Pin Connecting Capacitor...

  • Page 71: Adc Operation

    MC96F1206 User’s manual 11. 12-bit A/D Converter ADC Operation Figure 38. ADC Operation for Align bit...

  • Page 72: Figure 39. Converter Operation Flow

    11. 12-bit A/D Converter MC96F1206 User’s manual SET ADCM2 Select ADC Clock & Data Align bit. SET ADCM ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLG is set “1” and ADC AFLAG = 1? interrupt is occurred.

  • Page 73: Register Map

    MC96F1206 User’s manual 11. 12-bit A/D Converter Register map Table 14. ADC Register Map Name Address Direction Default Description ADCM A/D Converter Mode Register ADCM1 A/D Converter Mode 1 Register ADCRL A/D Converter Result Low Register ADCRH A/D Converter Result High Register...
  • Page 74 11. 12-bit A/D Converter MC96F1206 User’s manual NOTE) When using ports as ADC input port, set corresponding PSR2, PSR3 register to ADC input mode in order to open analog input switch and to prevent digital input. ADCRH (A/D Converter Result High Register) : 97H...
  • Page 75 MC96F1206 User’s manual 11. 12-bit A/D Converter VREF2P3SEL DSCHGEN LDOEN Initial value : 00H VREF2P3SE LDO output voltage select (Test only) 2.5V (default) About 2.3V DSCHGEN LDO Output Voltage Discharge Enable (Test only) Disable Enable LDOEN 2.5V LDO Enable Disable (default)

  • Page 76: Power Down Operation

    MC96F1206 User’s manual Power down operation The MC96F1206 has three power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, IDLE, STOP1 and STOP2 mode. In three modes, program is stopped.

  • Page 77: Idle Mode

    MC96F1206 User’s manual 12. Power-down operation IDLE mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.

  • Page 78: Release Operation Of Stop1,2 Mode

    12. Power-down operation MC96F1206 User’s manual Figure 41. STOP Mode Release Timing by External Interrupt Release operation of STOP1,2 mode After STOP1, 2 mode is released, the operation begins according to content of related interrupt register just before STOP1, 2 mode start (Figure 42). Interrupt Enable Flag of All (EA) of IE should be set to `1`.

  • Page 79: Register Map And Register Description For Power Down Operation

    MC96F1206 User’s manual 12. Power-down operation Register Map and Register Description for Power Down Operation Table 16. Power-down Operation Register Map Name Address Direction Default Description PCON Power control register Register description PCON (Power Control Register): 87H bit 7 bit 6...

  • Page 80: Reset Block Diagram

    13. Reset MC96F1206 User’s manual Reset The MC96F1206 has reset by external RESETB pin. The following is the hardware setting value. Table 18. Reset Value and the Relevant On Chip Hardware On Chip Hardware Reset Value Program Counter (PC) 0000H...

  • Page 81: Figure 44. Fast Vdd Rising Time

    MC96F1206 User’s manual 13. Reset Figure 44. Fast VDD Rising Time Figure 45. Internal Reset Release Timing on Power-Up Default 16ms @ WDTRC 8kHz Figure 46. Configuration Timing when Power-On...

  • Page 82: Figure 47. Boot Process Waveform

    13. Reset MC96F1206 User’s manual Relationship between VDD input and internal oscillator is described in figure 47 and table 19. Figure 47. Boot Process Waveform...

  • Page 83: Table 19. Boot Process Description

    MC96F1206 User’s manual 13. Reset Table 19. Boot Process Description Process Description Remark No operation ① -1st POR level Detection About 0.9~1.2V ② -Internal OSC (32MHz) ON -Delay section (=12ms) Slew rate >= 0.05V/ms ③ -VDD input voltage must rise over than...

  • Page 84: External Resetb Input

    13. Reset MC96F1206 User’s manual External RESETB input The External RESETB is the input to a Schmitt trigger. A reset in accomplished by holding the reset pin low for at least 10us over, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized.

  • Page 85: Low Voltage Indicator Processor

    Figure 50. Oscillator Generating Waveform Example Low Voltage Indicator Processor The MC96F1206 has an On-chip Low Voltage Indicator circuit for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the LVI can be selected by LVILS[2:0].

  • Page 86: 13.4.2 Internal Reset And Lvd Reset In Timing Diagram

    13. Reset MC96F1206 User’s manual 13.4.2 Internal reset and LVD reset in timing diagram Figure 52. Internal Reset at Power Fail Situation Register map Table 20. Reset Operation Register Map Name Address Direction Default Description RSFR Reset Source Flag Register...
  • Page 87 MC96F1206 User’s manual 13. Reset LVIR (LVI Control Register) : 8FH LVIINTON LVILS2 LVILS1 LVILS0 Initial value : 40H LVIINTON Select LVI reset or Interrupt Reset Interrupt LVILS[2:0] LVI level Voltage LVILS2 LVILS1 LVILS0 Description LVI disable (default) 2.1V LVI disable 2.5V...
  • Page 88 MC96F1206 User’s manual Flash memory MC96F1206 incorporates flash memory inside. Program can be written, erased, and overwritten on the flash memory while it is mounted on a board. The flash memory can be read by ‘MOVC’ instruction and programmed in OCD, serial ISP mode or user program mode. Followings are features summary of flash memory.

  • Page 89: Flash Program Rom Structure

    MC96F1206 User’s manual 14. Flash Memory Flash program ROM structure Figure 53. Flash Memory Map Figure 54.Address configuration of Flash memory...

  • Page 90: Register Map

    14. Flash memory MC96F1206 User’s manual Register map Table 21. Flash Memory Register Map Name Address Direction Default Description FEMR Flash Mode Register FECR Flash Control Register FESR Flash Status Register FETCR Flash Time Control Register FEARL Flash Address Low Register...
  • Page 91 MC96F1206 User’s manual 14. Flash Memory FECR (Flash Control Register) : EBH EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value : 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.

  • Page 92: Table 22. Program/Erase Time

    14. Flash memory MC96F1206 User’s manual FEARM (Flash address middle Register) : F3H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1 ARM0 Initial value : 00H ARM[7:0] Flash address middle FEARH (Flash address high Register) : F4H ARH7 ARH6 ARH5 ARH4...

  • Page 93: Serial In-System Program (Isp) Mode

    MC96F1206 User’s manual 14. Flash Memory Serial In-System Program (ISP) mode Serial in-system program uses the interface of debugger which uses two wires. Refer to Chapter 16. Development tools in details about debugger. 14.4.1 Flash operation Configuration (This Configuration is just used for follow description) FEMR[4]&[1]...

  • Page 94: Figure 56. The Sequence Of Bulk Erase Of Flash Memory

    14. Flash memory MC96F1206 User’s manual Figure 56. The sequence of bulk erase of Flash memory...

  • Page 95: 14.4.2 Flash Read

    MC96F1206 User’s manual 14. Flash Memory 14.4.2 Flash Read Step 1. Enter OCD(=ISP) mode. Step 2. Set ENBDM bit of BCR. Step 3. Enable debug and Request debug mode. Step 4. Read data from Flash. 14.4.3 Enable program mode Step 1. Enter OCD(=ISP) mode.

  • Page 96: 14.4.5 Flash Page Erase Mode

    14. Flash memory MC96F1206 User’s manual 14.4.5 Flash page erase mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:1000_1001 Step 4. Write ‘h00 to page buffer. (Data value is not important.) Step 5.

  • Page 97: 14.4.8 Flash Otp Area Write Mode

    MC96F1206 User’s manual 14. Flash Memory 14.4.8 Flash OTP area write mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:1000_1001 Step 4. Write data to page buffer.(Address automatically increases by twin.) Step 5.

  • Page 98: 14.4.12 Otp Program Verify Mode

    Load data to page buffer. Security MC96F1206 provides Lock bits which can be left unprogrammed (“0”) or can be programmed (“1”) to obtain the additional features listed in 24. The Lock bits can be erased to “0” with only the bulk erase command and a value of more than...

  • Page 99: Table 24.Security Policy Using Lock-Bits

    MC96F1206 User’s manual 14. Flash Memory Table 24.Security policy using lock-bits USER MODE ISP/PMODE LOCK MODE FLASH FLASH LOCKF  LOCKF: Lock bit of Flash memory  R: Read  W: Write  PE: Page erase  BE: Bulk Erase ...

  • Page 100: Electrical Characteristics

    15. Electrical characteristics MC96F1206 User’s manual Electrical characteristics Absolute maximum ratings Table 25.Absolute Maximum Ratings Parameter Rating Unit Note Supply Voltage -0.3~+6.5 – -0.3~VDD+0.3 Voltage on any pin with respect to VSS -0.3~VDD+0.3 Maximum current output sourced by (I I/O pin) Normal Voltage Pin ∑I...

  • Page 101: A/D Converter Characteristics

    MC96F1206 User’s manual 15. Electrical characteristics A/D Converter Characteristics (TA=-40℃ ~ +85℃, VDD= 2.2V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Resolution – – –- – Integral Non-Linearity – – ±4 Analog Reference Differential Non-Linearity – – ±1 Voltage = 2.5V ~ 5.5V. fx= Zero Offset Error –...

  • Page 102: Low Voltage Reset And Low Voltage Indicator Characteristics

    15. Electrical characteristics MC96F1206 User’s manual Low Voltage Reset and Low Voltage Indicator Characteristics =-40°C ~ +85°C, VDD=5.0V, VSS=0V) Table 29.LVR and LVI Characteristics Parameter Symbol Conditions Unit – 1.80 1.95 The LVR can select all levels Detection Level but LVI can select other levels except 1.80V...

  • Page 103: Internal Wdt Oscillator Characteristics

    MC96F1206 User’s manual 15. Electrical characteristics Internal WDT Oscillator Characteristics =-40°C ~ +85°C, VDD=2.2V ~ 5.5V, VSS=0V) Table 31.Internal WDT Oscillator Characteristics Parameter Symbol Conditions Unit Frequency – WDTRC Stabilization Time – – WDTS Enable – – WDTRC Current WDTRC Disable –...

  • Page 104: Ac Characteristics

    15. Electrical characteristics MC96F1206 User’s manual AC Characteristics = -40°C ~ +85°C, VDD=2.2V ~ 5.5V) Table 33.AC Characteristics Parameter Symbol Conditions Unit RESETB input low width Input, VDD=5V – Interrupt input high, low All interrupt, VDD=5V – – width External...

  • Page 105: Operating Voltage Range

    MC96F1206 User’s manual 15. Electrical characteristics Operating Voltage Range =1, 4, 8, 16 MHz) 16 MHz 1 MHz Supply voltage (V) Figure 58. Operating Voltage Range Typical Characteristics These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.

  • Page 106: Recommended Application Circuit

    15. Electrical characteristics MC96F1206 User’s manual Figure 61. Output High Voltage (VOH2) Figure 62.Power Supply Current (RUN, IDLE) Figure 63. Power Supply Current (STOP1, Figure 64. IRC Tolerance STOP2) Recommended Application Circuit For the microprocessor and other devices in the system to function correctly, it is also necessary to monitor the supply voltage during operations.

  • Page 107: Figure 65. Recommended Power Circuit Part When Using Dc Power

    MC96F1206 User’s manual 15. Electrical characteristics This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. 0.1uF 0.1uF The MCU power line (VDD and VSS) should be separated from the high- current part at a DC power node on the PCB layout.

  • Page 108: Development Tools

    MC96F1206 User’s manual Development tools This chapter introduces wide range of development tools for MC96F1206. ABOV offers software tools, debuggers, and programmers to help a user in generating right results to match target applications. ABOV supports entire development ecosystem of the customers.

  • Page 109: Programmer

    MC96F1206 User’s manual 16. Development tools Following is the OCD mode connections:  DSCL (MC96F1206 P12 port)  DSDA (MC96F1206 P13 port) Programmer E-PGM+ E-PGM+ is a single programmer, and allows a user to program on the device directly. •...

  • Page 110: Mtp Programming

    Figure 68. E-Gang4 and E-Gang6 (for Mass Production) MTP programming Program memory of MC96F1206 is an MTP Type. This flash is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. Table 35 introduces each pin and corresponding I/O status.

  • Page 111: Circuit Design Guide

    MC96F1206 User’s manual 16. Development tools The MC96F1206 needs only four signal lines including VDD and VSS pins for programming flash with serial protocol. Therefore the on-board programming is possible if the programming signal lines are considered when the PCB of application board is designed.

  • Page 112: Figure 70. On-Chip Debugging System In Block Diagram

    16. Development tools MC96F1206 User’s manual 36 introduces features of OCD and figure 118 shows a block diagram of the OCD interface and the On- chip Debug system. Table 36. Features of OCD Two wire external interface  1 for serial clock input ...

  • Page 113: 16.5.2 Two-Pin External Interface

    MC96F1206 User’s manual 16. Development tools 16.5.2 Two-pin external interface Basic transmission packet 10-bit packet transmission using two-pin interface.   1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.  Parity is even of ‘1’ for 8-bit data in transmitter.

  • Page 114: Figure 72. Data Transfer On Twin Bus

    16. Development tools MC96F1206 User’s manual Packet transmission timing Figure 72. Data Transfer on Twin Bus Figure 73. Bit Transfer on Serial Bus Figure 74. Start and Stop Condition...

  • Page 115: Figure 75. Acknowledge On Serial Bus

    MC96F1206 User’s manual 16. Development tools Figure 75. Acknowledge on Serial Bus Figure 76. Clock Synchronization during Wait Procedure...

  • Page 116: 16.5.3 Connection Of Transmission

    16. Development tools MC96F1206 User’s manual 16.5.3 Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). Figure 77. Connection of Transmission...

  • Page 117: Package Information

    MC96F1206 User’s manual 17. Package information Package information Figure 78. 20QFN Package Outline...

  • Page 118: Figure 79. 20 Tssop Package Outline

    17. Package information MC96F1206 User’s manual Figure 79. 20 TSSOP Package Outline...

  • Page 119: Figure 80. 16Sopn Package Outline

    MC96F1206 User’s manual 17. Package information Figure 80. 16SOPN Package Outline...

  • Page 120: Figure 81. Mc96F1206 Device Numbering Nomenclature

    6 Kbytes 256 bytes 15 inputs 20-TSSOP MC96F1206MBN 6 Kbytes 256 bytes 12 inputs 16-SOPN NOTE For more information on any aspect of this device, please contact your nearest distributor or ABOV sales office. Figure 81. MC96F1206 Device Numbering Nomenclature...

  • Page 121: Configure Option

    MC96F1206 User’s manual Appendix Appendix A. Configure option BSIZE[1] BSIZE[0] RSTEN LOCKB LOCKF Initial value : 00H BSIZE[1:0] Select Specific Area for Write Protection. NOTE) When LOCKB is set, it’s applied. 000h~7FFh (2KB) 000h~9FFh (2.5KB) 000h~BFFh (3KB) 000h~DFFh (3.5KB) RSTEN Select RESETB pin.

  • Page 122: Instruction Table

    Appendix MC96F1206 User’s manual B. Instruction table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column in tables shown below. • • Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following tables in this section.

  • Page 123: Table 39. Instruction Table: Logical

    MC96F1206 User’s manual Appendix Table 39. Instruction Table: Logical Logical Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...

  • Page 124: Table 40. Instruction Table: Data Transfer

    Appendix MC96F1206 User’s manual Table 40. Instruction Table: Data Transfer Data Transfer Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7...

  • Page 125: Table 41. Instruction Table: Boolean

    MC96F1206 User’s manual Appendix Table 41. Instruction Table: Boolean Boolean Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...

  • Page 126: Table 42. Instruction Table: Branching

    Appendix MC96F1206 User’s manual Table 42. Instruction Table: Branching Branching Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...

  • Page 127: Table 44. Instruction Table: Additional Instructions

    MC96F1206 User’s manual Appendix Table 44. Instruction Table: Additional Instructions Additional instructions (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP Software break command In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, and the register numbers of which are defined by the lowest three bits of the corresponding code.

  • Page 128: Flash Protection For Invalid Erase/ Write

    Appendix MC96F1206 User’s manual C. Flash protection for invalid erase/ write Appendix C shows example code to prevent code or data from being changed by abnormal operations such as noise, unstable power, and malfunction. Figure 82. Flash Protection against Abnormal Operations How to protect the flash Divide into decision and execution to Erase/Write in flash.

  • Page 129: Protection Flow Description

    — Set Flash Sector Address to Dummy Address  Sample Source — Refer to the ABOV website (www.abovsemi.com). — It is created based on the MC97F2664. — Each product should be modified according to the Page Buffer Size and Flash Size...

  • Page 130: Figure 83. Flowchart Of Flash Protection

    Appendix MC96F1206 User’s manual Start Initial Set LVR/LVI more than 2.0V Start Main Loop Working Write Flash? Set User_ID1 Working Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 Working Write Flash Set FEALH/M/L Set FEMR Check Flash A ddr...

  • Page 131: Other Protection By The Configure Options

    MC96F1206 User’s manual Appendix Other protection by the configure options  Protection by Configure option — Set flash protection by MCU Write Tool (OCD, PGM+, etc.) Vector Area: 00H~FFH Specific Area: 2KBytes (Address 000H – 07FFH) 2.5KBytes (Address 0000H – 09FFH) 3KBytes (Address 0000H –...

  • Page 132: Revision History

    Changed the body information of 20 QFN package from 4x4 mm to 3x3 mm. 2020-07-20 1.21 Corrected Internal RC oscillator to 32MHz at Table 1. MC96F1206 Device Features and Peripheral Counts. Corrected the values for block diagram at Figure 2. MC96F1206 Block Diagram.
  • Page 133 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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