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Abov MC97FG316 User Manual

16 mhz 8-bit microcontroller 16 kbytes flash memory, 512 bytes eeprom, 12-bit adc
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16 MHz 8-bit MC97FG316/MC97FG216 Microcontroller
16 Kbytes Flash memory, 512 bytes EEPROM, 12-bit ADC

Introduction

This document targets application developers who use MC97FG316/MC97FG216 for their specific
needs. This provides complete information of how to use MC97FG316/MC97FG216 devices. Standard
functions and blocks including corresponding register information of MC97FG316/MC97FG216 are
introduced in each chapter, while instruction set is in Appendix.
MC97FG316/MC97FG216 is based on M8051 core, and provides standard features of 8051 such as 8-
bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit
data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost effective solutions:
16Kbytes of FLASH, 256bytes of IRAM, 768bytes of XRAM, 512bytes of Data EEPROM, general
purpose I/O, basic interval timer, 8/16-bit timer/counter, watchdog timer, watch timer, SPI, USART, I2C,
on-chip POR, LVR, 12-bit A/D converter, analog comparator, buzzer driving port, 10-bit high speed
PWM output, on-chip oscillator and clock circuitry.
As a field proven best seller, MC97FG316/MC97FG216 has been sold more than 3 billion units up to
now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.

Reference document

MC97FG316/MC97FG216 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abovsemi.com
MC97FG316/MC97FG216
User's Manual Version 1.12

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Summary of Contents for Abov MC97FG316

  • Page 1: Introduction

    POR, LVR, 12-bit A/D converter, analog comparator, buzzer driving port, 10-bit high speed PWM output, on-chip oscillator and clock circuitry. As a field proven best seller, MC97FG316/MC97FG216 has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 12 Device overview ........................ 12 MC97FG316/MC97FG216 block diagram ................ 14 Pinouts and pin description ......................15 Pinouts ..........................15 Pin description ........................19 Port structures ..........................23 Memory organization ........................25 Program memory.......................
  • Page 3 MC97FG316/MC97FG216 User’s manual Contents Interrupt service routine address ..................61 Saving/restore general purpose registers ................. 61 6.10 Interrupt timing ........................62 6.11 Interrupt register overview ....................63 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ..........63 6.11.2 Interrupt Priority Register (IP, IP1, IP2 and IP3) ..........63 6.11.3 External Interrupt Flag Register (EIFLAG) ............
  • Page 4 Contents MC97FG316/MC97FG216 User’s manual 11.3.1 16-bit timer/counter mode................... 137 11.3.2 Register map ...................... 137 11.3.3 Timer 4 register description ................138 11.4 Timer interrupt status register (TMISR)................140 Buzzer driver ..........................141 12.1 Block diagram ........................143 12.2 Register map ........................143 12.3...
  • Page 5 MC97FG316/MC97FG216 User’s manual Contents 17.2 I2C bit transfer ......................... 183 17.3 Start/ repeated start/ stop ....................183 17.4 Data transfer ........................184 17.5 Acknowledge ........................185 17.6 Synchronization/ arbitration ..................... 186 17.7 Operation ......................... 187 17.7.1 Master transmitter ....................187 17.7.2 Master receiver ....................
  • Page 6 Contents MC97FG316/MC97FG216 User’s manual 21.7 Internal RC oscillator characteristics ................236 21.8 Ring-oscillator characteristics ..................237 21.9 PLL characteristics ......................237 21.10 DC characteristics ......................238 21.11 AC characteristics ......................239 21.12 SPI characteristics......................240 21.13 I2C characteristics ......................241 21.14 Main clock oscillator characteristics ................
  • Page 7 List of figures List of figures Figure 1. MC97FG316/MC97FG216 Block Diagram ................14 Figure 2. MC97FG316 32LQFP Pin Assignment .................. 15 Figure 3. MC97FG316 32QFN Pin Assignment ..................16 Figure 4. MC97FG316 28TSSOP Pin Assignment ................17 Figure 5. MC97FG216 20TSSOP Pin Assignment ................18 Figure 6.
  • Page 8 List of figures MC97FG316/MC97FG216 User’s manual Figure 49. PLL Frequency Flow Chart ....................120 Figure 50. 8-bit Timer/Event Counter2, 3 Block Diagram ..............123 Figure 51. Timer/Event Counter2, 3 Example ..................124 Figure 52. Operation Example of Timer/Event Counter2, 3 ..............124 Figure 53.
  • Page 9 Figure 125. 28 TSSOP Package Outline .................... 250 Figure 126. 20 TSSOP Package Outline .................... 251 Figure 127. MC97FG316/MC97FG216 Device Numbering Nomenclature ........252 Figure 128. Debugger (OCD2) and Pinouts..................253 Figure 129. E-PGM+ (Single Writer) and Pinouts ................254 Figure 130.
  • Page 10 List of tables MC97FG316/MC97FG216 User’s manual List of tables Table 1. MC97FG316/MC97FG216 Device Features and Peripheral Counts ........12 Table 2. Normal Pin Description ......................19 Table 3. SFR Map Summary ......................... 30 Table 4. XSFR Map Summary ......................31 Table 5.
  • Page 11 Table 52. I2C Characteristics ......................241 Table 53. Main Clock Oscillator Characteristics .................. 242 Table 54. Sub Clock Oscillator Characteristics ................... 242 Table 55. MC97FG316/MC97FG216 Device Ordering Information ............ 252 Table 56. Pins for Flash Programming ....................255 Table 57. OCD II Features ........................257 Table 58.

  • Page 12: Description

    1. Description MC97FG316/MC97FG216 User’s manual Description MC97FG316/MC97FG216 is an advanced CMOS 8-bit microcontroller with 16Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. Device overview In Table 1, features of MC97FG316/MC97FG216 and peripheral counts are introduced.
  • Page 13 MC97FG316/MC97FG216 User’s manual 1. Description Table 1. MC97FG316/MC97FG216 Device Features and Peripheral Counts (continued) Peripherals Description On chip analog comparator 1-ch Analog comparator  STOP1, STOP2 mode Power down mode  IDLE mode General Purpose I/O (GPIO)  30Ports (P0[7:0], P1[6:0], P2[6:0], P3[7:0]): 32-Pin ...

  • Page 14: Mc97Fg316/Mc97Fg216 Block Diagram

    1. Description MC97FG316/MC97FG216 User’s manual MC97FG316/MC97FG216 block diagram In this section, MC97FG316/MC97FG216 device with peripherals are described in a block diagram. DSCL/P06 DSDA/P07 P25/AN14 P24/AN13 P23/AN12 On-Chip P37/AN11 P06~P00 PORT Debug P36/AN10 P16/AN9 P15/AN8 12-BIT P07/AN7 P16~P10 PORT M8051 P06/AN6...

  • Page 15: Pinouts And Pin Description

    MC97FG316/MC97FG216 User’s manual 2. Pinouts and pin description Pinouts and pin description In this chapter, MC97FG316/MC97FG216 device pinouts and pin descriptions are introduced. Pinouts (DSCL)/ACOUT/AN6/T0O/SCL/P06 P01 / ACK0 / SCK0 / AN1 (DSDA) / AN7 / EC0 / SDA / P07...

  • Page 16: Figure 3. Mc97Fg316 32Qfn Pin Assignment

    PWM1AA / T1O / INT0 / P10 P22 / RESETB PWM1AB / INT1 / P11 P21 / XOUT PWM1BA / BUZ / INT2 / P12 P20 / XIN NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[7:6] pin as DSDA, DSCL. Figure 3. MC97FG316 32QFN Pin Assignment...

  • Page 17: Figure 4. Mc97Fg316 28Tssop Pin Assignment

    PWM1CA / (EC0) / P14 P37 / RxD1 / AN11 AN8 / PWM1CB / P15 P36 / TxD1 / AN10 SS1 / P34 P35 / ACK1 NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[7:6] pin as DSDA, DSCL. Figure 4. MC97FG316 28TSSOP Pin Assignment...

  • Page 18: Figure 5. Mc97Fg216 20Tssop Pin Assignment

    2. Pinouts and pin description MC97FG316/MC97FG216 User’s manual SXIN / AC+ / AN4 / P04 P03 / RxD0 / MISO0 / EC2 / AN3 SXOUT / AC- / AN5 / P05 P02 / TxD0 / MOSI0 / T2O / AN2...

  • Page 19: Pin Description

    MC97FG316/MC97FG216 User’s manual 2. Pinouts and pin description Pin description Table 2. Normal Pin Description Pin no. Description Remark Name LQFP TSSOP TSSOP P00* IOUS Port 0 bit 0 Input/output USART0 slave select signal ADC input ch-0 AVref A/D converter reference voltage...
  • Page 20 2. Pinouts and pin description MC97FG316/MC97FG216 User’s manual Table 2. Normal Pin Description (continued) Pin no. Description Remark Name LQFP TSSOP TSSOP IOUS P07* Port 0 bit 7 Input/output I2C data signal Timer 0 event counter input ADC input ch-7...
  • Page 21 MC97FG316/MC97FG216 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Pin no. Description Remark Name LQFP TSSOP TSSOP P21* IOUS Port 2 bit 1 Input/output XOUT Main oscillator output P22* IOUS Port 2 bit 2 Input/output...
  • Page 22 2. Pinouts and pin description MC97FG316/MC97FG216 User’s manual NOTES: At 28TSSOP PKG, P2[6:3] in 32-pin package is removed and their functions are not allowed. At 20TSSOP PKG, P2[6:3] and P3[7:0] in 32-pin package are removed and their functions are not allowed.

  • Page 23: Port Structures

    MC97FG316/MC97FG216 User’s manual 3. Port structures Port structures In this chapter, two port structures are introduced in Figure 6 and Figure 7 regarding general purpose I/O port and external interrupt I/O port respectively. LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V)

  • Page 24: Figure 7. External Interrupt I/O Port

    3. Port structures MC97FG316/MC97FG216 User’s manual LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR...

  • Page 25: Memory Organization

    (XRAM) is 768bytes and internal EEPROM is 512bytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and MC97FG316/MC97FG216 has just 16Kbytes program memory space. Figure 8 shows a map of the lower part of the program memory.

  • Page 26: Figure 8. Program Memory Map

    4. Memory organization MC97FG316/MC97FG216 User’s manual FFFFH 4000H Configuration Option Mirror 3FFFH Program Memory Areas 16Kbytes Interrupt Vector Areas 0000H NOTES: The 16Kbytes includes the Interrupt Vector Region. The value of Configuration Option can be read at address 0x4000. Non-volatile and reprogramming memory: Flash memory based on EEPROM cell...

  • Page 27: Data Memory

    MC97FG316/MC97FG216 User’s manual 4. Memory organization Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of 256bytes. In fact, the addressing modes for the internal data memory can accommodate up to 384bytes by using a simple trick.

  • Page 28: Figure 10. Lower 128Bytes Of Ram

    4. Memory organization MC97FG316/MC97FG216 User’s manual 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 29: Eeprom Data Memory And External Data Memory

    4. Memory organization EEPROM data memory and external data memory MC97FG316/MC97FG216 has 512bytes of EEPROM, 768bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. For more information about EEPROM Data memory, see 20. Memory programming.

  • Page 30: Sfr Map

    4. Memory organization MC97FG316/MC97FG216 User’s manual SFR map 4.4.1 SFR map summary Table 3. SFR Map Summary Reserved M8050 Compatible 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH ACCSR UCTRL11 UCTRL12 UCTRL13 USTAT1 UBAUD1 UDATA1 FEARL FEARM FEARH FEDR FEMR...

  • Page 31: Table 4. Xsfr Map Summary

    MC97FG316/MC97FG216 User’s manual 4. Memory organization Table 4. XSFR Map Summary 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH 2F58H 2F50H FUSE_CONF 2F48H 2F40H 2F38H 2F30H 2F28H 2F20H 2F18H 2F10H PSR0 PSR1 PSR2 WDTC WDTSR WDTCNTH WDTCNTL 2F08H P0DB P1DB...

  • Page 32: Sfr Map

    4. Memory organization MC97FG316/MC97FG216 User’s manual 4.4.2 SFR map Table 5. SFR Map Addr. Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 33 MC97FG316/MC97FG216 User’s manual 4. Memory organization Table 5. SFR Map (continued) Addr. Function Symbol @Reset Interrupt Priority Register 1 High IP1H Interrupt Priority Register 2 Interrupt Priority Register 2 High IP2H Interrupt Priority Register 3 Interrupt Priority Register 3 High...
  • Page 34 4. Memory organization MC97FG316/MC97FG216 User’s manual Table 5. SFR Map (continued) Addr. Function Symbol @Reset Timer 1 PWM Control Register 3 T1PCR3 PWM1 Non-Overlap Delay Register T1DLYA for ch. A/AB A/D Converter Mode Register ADCM A/D Converter Mode 2 Register...
  • Page 35 MC97FG316/MC97FG216 User’s manual 4. Memory organization Table 5. SFR Map (continued) Addr. Function Symbol @Reset SCL Low Period Register I2CSCLL SCL High Period Register I2CSCLH SDA Hold Time Register I2CSDAH I2C Data Register I2CDR Accumulator USART Control 1 Register 0...
  • Page 36 4. Memory organization MC97FG316/MC97FG216 User’s manual Table 5. SFR Map (continued) Addr. Function Symbol @Reset 2F00H Pull-up Resistor Selection P0PU Register 2F01H Pull-up Resistor Selection P1PU Register 2F02H Pull-up Resistor Selection P2PU Register 2F03H Pull-up Resistor Selection P3PU Register 2F04H...

  • Page 37: Compiler Compatible Sfr

    MC97FG316/MC97FG216 User’s manual 4. Memory organization 4.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 38 4. Memory organization MC97FG316/MC97FG216 User’s manual DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...
  • Page 39 MC97FG316/MC97FG216 User’s manual 4. Memory organization XBANK (XRAM Bank Pointer): A0H XBANK Initial value: 00H XBANK XRAM Bank Pointer NOTES: This XBANK register holds the [15:8] part of memory address during access to data. Address[15:0]: “XBANK:Ri” (R1: R0 or R1)

  • Page 40: O Ports

    MC97FG316/MC97FG216 User’s manual I/O ports MC97FG316/MC97FG216 has four groups of I/O ports (P0 ~ P3). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. P0 includes a function that can generate interrupt signals according to state of a pin.

  • Page 41: Port Selection Register (Psrx)

    MC97FG316/MC97FG216 User’s manual 5. I/O ports 5.1.7 Port selection register (PSRx) PSRx registers prevent the input leakage current when ports are connected to analog inputs. If the bit of PSRx is ‘1’, the dynamic current path from the Schmitt OR gate of the port is cut off and the digital input of the corresponding port is always ‘1’.

  • Page 42: P0 Port

    5. I/O ports MC97FG316/MC97FG216 User’s manual P0 port 5.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), P0 pull-up resistor selection register (P0PU), P0 open-drain selection register (P0OD), debounce enable register (P0DB) and pin change interrupt register (PCI0).
  • Page 43 MC97FG316/MC97FG216 User’s manual 5. I/O ports P0DB (P0 De-bounce Enable Register): 2F08H P07DB P06DB P05DB P04DB P03DB P02DB P01DB P00DB Initial value: 00H P0DB[7:0] Configure De-bounce Clock of P0 Port Disable Enable - De-bounce clock of port is about 1MHz/4(about 4us)
  • Page 44 5. I/O ports MC97FG316/MC97FG216 User’s manual PSR2 (USART0, TIMER0 Port Selection Register): 2F12H PSR20 Initial value: 00H PSR2[0] RxD0, TxD0, EC0, T0O ports selection register P0[3:2] for RxD0, TxD0 (default) P0[7:6] for EC0, T0O P3[3:2] for RxD0, TxD0 P1[4:3] for EC0, T0O...

  • Page 45: P1 Port

    MC97FG316/MC97FG216 User’s manual 5. I/O ports P1 port 5.3.1 P1 port description P1 is a 7-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), P1 pull-up resistor selection register (P1PU), P1 open-drain selection register (P1OD) and debounce enable register (P1DB).
  • Page 46 5. I/O ports MC97FG316/MC97FG216 User’s manual P1DB (P1 De-bounce Enable Register): 2F09H P16DB P15DB P14DB P13DB P12DB P11DB P10DB Initial value: 00H P1DB[7:0] Configure De-bounce Clock of P1 Port Disable Enable - De-bounce clock of port is about 1MHz/4(about 4us)

  • Page 47: P2 Port

    MC97FG316/MC97FG216 User’s manual 5. I/O ports P2 port 5.4.1 P2 port description P2 is a 7-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU), P2 open-drain selection register (P2OD) and debounce enable register (P2DB).
  • Page 48 5. I/O ports MC97FG316/MC97FG216 User’s manual P2DB (P2 De-bounce Enable Register): 2F0AH P26DB P25DB P24DB P23DB P22DB P21DB P20DB Initial value: 00H P2DB[6:0] Configure De-bounce Clock of P2 Port Disable Enable - De-bounce clock of port is about 1MHz/4(about 4us)

  • Page 49: P3 Port

    MC97FG316/MC97FG216 User’s manual 5. I/O ports P3 port 5.5.1 P3 port description P3 is an 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO), P3 pull-up resistor selection register (P3PU) and debounce enable register (P3DB). Refer to the port selection registers for the P1, P2, P3 and P3 function selection.
  • Page 50 5. I/O ports MC97FG316/MC97FG216 User’s manual P3DB (P3 De-bounce Enable Register): 2F0BH P37DB P36DB P35DB P34DB P33DB P32DB P31DB P30DB Initial value: 00H P3DB[7:0] Configure De-bounce Clock of P3 Port Disable Enable - De-bounce clock of port is about 1MHz/4(about 4us)

  • Page 51: Port Noise Canceller

    MC97FG316/MC97FG216 User’s manual 5. I/O ports Port noise canceller Figure 12 is the Noise canceller time diagram for Noise cancel of Port. It has the Noise cancel value is about 4us to Port input. t < T t < T t >...

  • Page 52: Interrupt Controller

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual Interrupt controller MC97FG316/MC97FG216 supports up to 24 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. In addition, they have four levels of priority assigned to themselves. A non-maskable interrupt source is always enabled with a higher priority than any other interrupt sources, and is not controllable by software.

  • Page 53: Figure 13. Interrupt Group Priority Level

    MC97FG316/MC97FG216 User’s manual 6. Interrupt controller Figure 13 shows INT10 is higher priority small than any interrupt (Priority order: INT10 > INT4 > INT19 > INT0 > INT1 > ~~ > INT23). ( IP, IPH ) ( IP1, IP1H )

  • Page 54: External Interrupt

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual External interrupt External interrupts on INT0, INT1, INT2, INT3, INT4, INT5, INT6 and INT7 pins receive various interrupt requests depending on the external interrupt edge register (EIEDGE), the external interrupt polarity register (EIPOLA) and the external interrupt both edge register (EIBOTH) as shown in Figure 14.

  • Page 55: Block Diagram

    MC97FG316/MC97FG216 User’s manual 6. Interrupt controller Block diagram IP3[9E IP3H[9F IP2[9C IP2H[9D IP1[9A IP1H[9B EIEDGE[A5 EIPOLA[A6 IE0[A8 IP[92 IPH[93 EIBOTH[A7 EIFLAG.0 [A4 FLAG0 INT0 Priority High EIFLAG.1 [A4 FLAG1 INT1 EIFLAG.2 [A4 INT2 FLAG2 EIFLAG.3 [A4 INT3 FLAG3 INT4 EIFLAG.4 [A4...
  • Page 56 6. Interrupt controller MC97FG316/MC97FG216 User’s manual NOTES: The release signal for stop/idle mode may be generated by all interrupt sources which are enabled without reference to the priority level. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register.

  • Page 57: Interrupt Vector Table

    6. Interrupt controller Interrupt vector table Interrupt controller of MC97FG316/MC97FG216 supports 24 interrupt sources as shown in Table 7. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 58: Interrupt Sequence

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.

  • Page 59: Effective Timing After Controlling Interrupt Bit

    MC97FG316/MC97FG216 User’s manual 6. Interrupt controller Effective timing after controlling interrupt bit Case A in Figure 17 shows the effective time after controlling Interrupt Enable Registers (IE, IE1, IE2, and IE3). Interrupt Enable Register command After executing IE set/clear, enable register is effective.

  • Page 60: Multi-Interrupt

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual Multi-interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 61: Interrupt Enable Accept Timing

    MC97FG316/MC97FG216 User’s manual 6. Interrupt controller Interrupt enable accept timing System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 20. Interrupt Response Timing Diagram Interrupt service routine address...

  • Page 62: Interrupt Timing

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual 6.10 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: ...

  • Page 63: Interrupt Register Overview

    MC97FG316/MC97FG216 User’s manual 6. Interrupt controller 6.11 Interrupt register overview 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) Interrupt Enable Register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt.

  • Page 64: Register Map

    6. Interrupt controller MC97FG316/MC97FG216 User’s manual 6.11.8 Register map Table 8. Interrupt Register Map Name Address Direction Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register Interrupt Priority Register High...
  • Page 65 MC97FG316/MC97FG216 User’s manual 6. Interrupt controller IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 5...
  • Page 66 6. Interrupt controller MC97FG316/MC97FG216 User’s manual IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable USART1 Tx Interrupt Disable Enable INT10E Enable or Disable USART1 Rx Interrupt...
  • Page 67 MC97FG316/MC97FG216 User’s manual 6. Interrupt controller IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable External Interrupt 6 Disable Enable INT16E Enable or Disable Timer 4 Match Interrupt...
  • Page 68 6. Interrupt controller MC97FG316/MC97FG216 User’s manual IE3 (Interrupt Enable Register 3): ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value: 00H INT23E Enable or Disable Pin Change Interrupt 0 (Port 0) Disable Enable INT22E Enable or Disable BIT Interrupt...
  • Page 69 MC97FG316/MC97FG216 User’s manual 6. Interrupt controller IP1 (Interrupt Priority Register 1): 9AH – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP1H (Interrupt Priority Register 1 High): 9BH – – IP1H5 IP1H4 IP1H3 IP1H2 IP1H1 IP1H0 –...
  • Page 70 6. Interrupt controller MC97FG316/MC97FG216 User’s manual IP3 (Interrupt Priority Register 3): 9EH – – IP35 IP34 IP33 IP32 IP31 IP30 – – Initial value: 00H IP3H (Interrupt Priority Register 3 High): 9FH – – IP3H5 IP3H4 IP3H3 IP3H2 IP3H1 IP3H0 –...
  • Page 71 MC97FG316/MC97FG216 User’s manual 6. Interrupt controller EIPOLA (External Interrupt Polarity Register): A6H POLA7 POLA6 POLA5 POLA4 POLA3 POLA2 POLA1 POLA0 Initial value: 00H POLA[7:0] According to EIEDGE, External interrupt polarity register has a different means. If EIEDGE is level type, external interrupt polarity is able to have Low/High level value.

  • Page 72: Clock Generator

    7. Clock generator MC97FG316/MC97FG216 User’s manual Clock generator As shown in Figure 24, a clock generator produces basic clock pulses which provide a system clock for CPU and peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock can operate easily by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.

  • Page 73: Clock Generator Block Diagram

    MC97FG316/MC97FG216 User’s manual 7. Clock generator Clock generator block diagram In this section, a clock generator of MC97FG316/MC97FG216 is described in a block diagram. PDOWN Main DCLK System SCLK ClockGen . (Core,System, Peripherals) Clock XOUT Change & DIV System Clock...

  • Page 74: Register Description

    7. Clock generator MC97FG316/MC97FG216 User’s manual Register description The Clock Generation Register uses clock control for system operation. The clock generation consists of System and Clock register. SCCR (System and Clock Control Register): 8AH STOP1 DIV1 DIV0 CBYS ISTOP XSTOP...
  • Page 75 MC97FG316/MC97FG216 User’s manual 7. Clock generator fSUB (32.768kHz) fRING/8 (125kHz)

  • Page 76: Basic Interval Timer (Bit)

    MC97FG316/MC97FG216 User’s manual Basic Interval Timer (BIT) MC97FG316/MC97FG216 has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for watchdog timer counting, and provides a basic interval timer interrupt (BITF). BIT of MC97FG316/MC97FG216 features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 77: Bit Register Description

    MC97FG316/MC97FG216 User’s manual 8. Basic Interval Timer (BIT) BIT register description The Basic Interval Timer Register consists of Basic Clock control register (BCCR) and Basic Interval Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared as ‘0’...

  • Page 78: Watchdog Timer (Wdt)

    9. Watchdog Timer (WDT) MC97FG316/MC97FG216 User’s manual Watchdog Timer (WDT) Watchdog Timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 79: Setting Window Open Period Of Wdt

    MC97FG316/MC97FG216 User’s manual 9. Watchdog Timer (WDT) Setting window open period of WDT The window open period of the watchdog timer can select as 50%, 75%, and 100% by WINDOW [1:0] of WDTCR. If the data “96H” is written to the WDTC register during a window close period, watchdog reset is occurred.

  • Page 80: Wdt Block Diagram

    9. Watchdog Timer (WDT) MC97FG316/MC97FG216 User’s manual Table 11. Setting Window Open Period of WDT Setting of window open period Window close period Window open period 50%, WINDOW[1:0]=00b & WDTPDON = 1 75%, WINDOW[1:0]=01b & WDTPDON = 1 100%, WINDOW[1:0]=10b & WDTPDON = 1 WDTCNT = “0000H”...

  • Page 81: Register Map

    MC97FG316/MC97FG216 User’s manual 9. Watchdog Timer (WDT) Register map Table 12. Watchdog Timer Register Map Name Address Direction Default Description WDTC 2F14H Watch Dog Timer Clear Register WDTSR 2F15H Watch Dog Timer Status Register WDTIDR Watch Dog Timer Identification Register...
  • Page 82 9. Watchdog Timer (WDT) MC97FG316/MC97FG216 User’s manual WDTSR (Watch Dog Timer Status Register): 2F15H WSTATE WDTIFR Initial value: 00H WSTATE Window Status. Close window Open window When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write WDTIFR ‘0’ to this bit or auto clear by INT_ACK signal.
  • Page 83 MC97FG316/MC97FG216 User’s manual 9. Watchdog Timer (WDT) WDTCR (Watch Dog Timer Control Register): 8DH WDTEN WDTRTI WDTPDON WINDOW1 WINDOW0 WDOVF2 WDOVF1 WDOVF0 Initial value: 07H WDTEN Control WDT Operation Disable (WDTRC Stop) Enable WDTRTI 3/4 Interval interrupt Disable (WDT overflow reset used)

  • Page 84: Watch Timer (Wt)

    7-bit counter in order to increase resolution. In WTR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. 10.1 WT block diagram A WDT of MC97FG316/MC97FG216 is described in a block diagram. Match Clear 14Bit...

  • Page 85: Register Map

    MC97FG316/MC97FG216 User’s manual 10. Watch Timer (WT) 10.2 Register map Table 13. Watch Timer Register Map Name Address Direction Default Description WTCR Watch Timer Counter Register Watch Timer Register WTMR Watch Timer Mode Register 10.3 WT register description WTCR (Watch Timer Counter Register: Read Case): 96H –...
  • Page 86 10. Watch Timer (WT) MC97FG316/MC97FG216 User’s manual WTMR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’...

  • Page 87: Timer/Pwm

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM Timer/PWM 11.1 8-bit timer/event counter 0, 1 Timer 0 and timer 1 can be used as either two 8-bit timer/counter or one 16-bit timer/counter by combining them. Each 8-bit timer/event counter consists of a multiplexer, a timer data register, a counter register, a mode register, an input capture register and a comparator.

  • Page 88: Table 14. Timer 0, 1 Operating Modes

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Table 14. Timer 0, 1 Operating Modes 16BIT CAP0 CAP1 PWM1E T0CK[2:0] T1CK[3:0] T0/1_PE Timer 0 Timer 1 XXXX 8-bit Timer 8-bit Timer XXXX 8-bit Event 8-bit Capture Counter XXXX 8-bit Capture 8-bit Compare Output...

  • Page 89: 8-Bit Timer/Counter Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 8-bit timer/counter mode 11.1.1 The 8-bit Timer/Counter Mode is selected by control registers as shown in Figure 29. ADDRESS: B2 T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST T0CR INITIAL VALUE: 0000_0000 16BIT CAP1 T1CN...

  • Page 90: Figure 30. Timer/Event Counter 0, 1 Example

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Match with T0DR/T1DR T0DR/T1DR Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 0, 1 (T0IF, T1IF) Interrupt Occur Occur Occur Interrupt Interrupt Interrupt Figure 30. Timer/Event Counter 0, 1 Example T0DR/T1DR Value...

  • Page 91: 16-Bit Timer/Counter Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 16-bit timer/counter mode 11.1.2 The timer register runs with all 16 bits. A 16-bit timer/counter register T0, T1 are incremented from 0003H to FFFFH until it matches T0DR, T1DR to reset 0000H. The match output generates the Timer 0 interrupt (No timer 1 interrupt).

  • Page 92: Figure 33. 8-Bit Capture Mode For Timer 0, 1

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual ADDRESS: B2 T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST T0CR INITIAL VALUE: 0000_0000 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 ADDRESS: B4 T1CR INITIAL VALUE: 0000_0000 T0ST T0CN ÷2 8-bit Timer0 Counter ÷4 Clear ÷8...

  • Page 93: Figure 34. Input Capture Mode Operation Of Timer 0, 1

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM CDR0, CDR1 Load T0/T1 Value Count Pulse Period Up-count TIME Ext. INT0,1 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period Figure 34. Input Capture Mode Operation of Timer 0, 1 Figure 35. Express Timer Overflow in Capture Mode...

  • Page 94: 16-Bit Capture Mode

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 16-bit capture mode 11.1.4 The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The clock source is selected from T0CK[2:0] and T1CK[3:0] must set 1111b and 16BIT bit must set to ‘1’.

  • Page 95: Pwm Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.1.5 PWM mode The timer 1 has a high speed PWM (pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM1E to ‘1’.

  • Page 96: Figure 37. Pwm Mode (Force 6-Ch)

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 ADDRESS: B4 T1CR INITIAL VALUE: 0000_0000 ESYN NOPS NOPS BMOD PHLT UPDT UALL ADDRESS: B7 T1PCR INITIAL VALUE: 0000_0000 FORC FORC PABO PBBO ADDRESS: BD PAOE PBOE...

  • Page 97: Figure 38. Pwm Mode (Force All-Ch)

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 ADDRESS: B4 T1CR INITIAL VALUE: 0000_0000 ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 ADDRESS: B7 T1PCR INITIAL VALUE: 0000_0000 ADDRESS: BD FORCA FORC6 PAOE PABOE PBOE PBBOE...

  • Page 98: Figure 39. Example Of Pwm At 4Mhz

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Source Clock P10/PWM POLA = 1 P10/PWM POLA = 0 Duty Cycle(1+80 )X250ns = 32.25us Period Cycle(1+3FF )X250ns = 256us → 3.9kHz PPR9 PPR8 T1PPRL(8-bit) T1CR[1:0] = 00 T1PPRH = 03 T1PPRL = FF T1ADRH = 00...

  • Page 99: Figure 41. Example Of Pwm Output Waveform

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM Phase correction & Frequency correction On operating PWM, the phase and the frequency can be changed by using BMOD bit (back-to-back mode) in T1PCR register (Refer to Figure 41, Figure 42, and Figure 43). In the back-to-back mode, the counter of PWM repeats up/down count. In fact, the effective duty and period becomes twofold of the register set values (Refer to Figure 41 and Figure 42).

  • Page 100: Figure 43. Example Of Phase Correction And Frequency Correction Of Pwm

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Duty, Period Update Back-to-Back mode Output Duty1 Duty2 Duty3 Period1 Period2 Period3 Interrupt Timing Overflow INT. Overflow INT. Bottom INT. Overflow INT. Figure 43. Example of Phase Correction and Frequency Correction of PWM External Sync If using ESYNC bit of T1PCR register, it is possible to synchronize the output of PWM from external signal.

  • Page 101: Figure 44. Example Of Pwm External Synchronization With Blnkb Input

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1PPRH = 02 (ESYNC=1) T1PPRL = 2A T1ADRH = 00 BLNKB “0” T1ADRL = 12 PWM STOP BLNKB “1” PWM Restart Source Clock P10/PWM POLA = 1 Counter Stop BLNKB ESYNC = 1 Figure 44. Example of PWM External Synchronization with BLNKB Input FORCE Drive ALL ch with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs...

  • Page 102: Figure 45. Example Of Force Drive All-Ch With A-Ch

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual ADDRESS: BD FORCA FORC6 PAOE PABOE PBOE PBBOE PCOE PCOE T1PCR2 INITIAL VALUE: 0000_0000 PWMA PAOE PWMOA PABOE /PWMOA PBOE PWMOB PBBOE /PWMOB ※C-ch operation is the same with channel A and B waveform Figure 45. Example of Force Drive All-ch with A-ch FORCE 6-ch Drive If FORC6 bit sets to ‘1’, it is possible to enable or disable PWM output pin and inversion output pin...

  • Page 103: Figure 46. Example Of Force Drive 6-Ch Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM ADDRESS: BD FORCA FORC6 PAOE PABOE PBOE PBBOE PCOE PCOE T1PCR2 INITIAL VALUE: 0000_0000 PWMA PAOE PWMOA PABOE /PWMOA PWMB PBOE PWMOB PBBOE /PWMOB ※C-ch operation is the same with channel A and B waveform...

  • Page 104: Figure 47. Pwm Port Control

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual ADDRESS: B4 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 T1CR INITIAL VALUE: 0000_0000 ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 ADDRESS: B7 T1PCR INITIAL VALUE: 0000_0000 ADDRESS: BD FORCA FORC6 PAOE PABOE PBOE PBBOE PCOE...

  • Page 105: Figure 48. Example Of Pwm Delay

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM ADDRESS: BD FORCA FORC6 PAOE PABOE PBOE PBBOE PCOE PCOE T1PCR2 INITIAL VALUE: 0000_0000 POCO PLLPD T1_PE POLA POLB POLC HCKE ADDRESS: BE T1PCR3 INITIAL VALUE: 0000_00-0 DLYA3 DLYA2 DLYA1 DLYA0 ADDRESS: BF T1DLYA INITIAL VALUE: 0000_0000...

  • Page 106: 8-Bit (16-Bit) Compare Output Mode

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 11.1.6 8-bit (16-bit) compare output mode If the T1 (T0+T1) value and the T1DR (T0DR+T1DR) value are matched, T1/PWM1A port outputs. The output is 50:50 of duty square wave, the frequency is following. To export the compare output as T1/PWM1A, the T1_PE bit in the T1PCR3 register must set to ‘1’.

  • Page 107: Timer/Counter 0 Register Description

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.1.8 Timer/counter 0 register description The Timer/Counter 0,1 register consists of Timer 0 Mode Control Register (T0CR), Timer 0 Register (T0), Timer 0 Data Register (T0DR), Capture 0 Data Register (CDR0), Timer 1 Mode Control Register...
  • Page 108 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T0 (Timer 0 Register: Read Case): B3H Initial value: 00H T0[7:0] T0 Counter T0DR (Timer 0 Data Register: Write Case): B3H T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value: FFH T0D[7:0] T0 Compare...
  • Page 109 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1CR (Timer 1 Mode Count Register): B4H 16BIT CAP1 T1CN T1ST T1CK3 T1CK2 T1CK1 T1CK0 Initial value: 00H 16BIT Select Timer 1 8/16-bit 8-bit 16-bit CAP1 Control Timer 1 operation mode Timer/Counter mode Capture mode...
  • Page 110 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T1DR (Timer 1 Data Register: Write Case): B5H T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value: FFH T1D[7:0] T1 Compare T1PPRH (Timer 1 PWM Period High Register: Write Case PWM mode only): B6H...
  • Page 111 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1ADRL (Timer 1 PWM 1A Duty Low Register PWM mode only): B0H PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 Initial value: 7FH T1ADR[7:0] T1 PWM Duty NOTE: Only write, when PWM1E ‘1’ CDR1 (Capture 1 Data Register: Read Case, Capture mode only): B0H...
  • Page 112 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T1PCR (Timer 1 PWM Control Register): B7H PWM1E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 Initial value: 00H PWM1E Control PWM PWM disable PWM enable ESYNC Select the operation of External Sync Mode External Sync Mode disable...
  • Page 113 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1BDRH (Timer 1 PWM 1B Duty High Register): BAH PBD9 PBD8 Initial value: 00H T1BDR[9:8] PWM 1B ch Duty NOTE: Only write, when PWM1E ‘1’ T1BDRL (Timer 1 PWM 1B Duty Low Register): B9H PBD7...
  • Page 114 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T1PCR2 (Timer 1 PWM Control Register 2): BDH FORCA FORC6 PAOE PABOE PBOE PBBOE PCOE PCBOE Initial value: 00H FORCA Control Force Drive A Channel mode Force Drive A Channel mode disable Force Drive A Channel mode enable...
  • Page 115 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1PCR3 (Timer 1 PWM Control Register 3): BEH T1_PE POLA POLB POLC POCON HCKE PLLPDB Initial value: 00H T1_PE Control Timer1/PWM1 Output port T1, PWM1 Output operation disable T1, PWM1 Output operation enable POLA Configure PWM A-ch polarity...
  • Page 116 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T1DLYA (PWM1 Non-Overlap Delay Register for channel A/AB): BFH DLYA3 DLYA2 DLYA1 DLYA0 DLYAB3 DLYAB2 DLYAB1 DLYAB0 Initial value: 00H DLYA[3:0] PWM A channel Output Delay (Rising edge only) DLYAB[3:0] PWM AB channel Output Delay (Rising edge only)
  • Page 117 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T1ISR (Timer 1 Interrupt Status Register): C4H IOVR IBTM ICMA ICMB ICMC ICAP Initial value: 00H IOVR Overflow (match with T1DR in Timer mode or T1PPR in PWM mode) interrupt status NOTE: For clear, write ‘1’ to this bit...
  • Page 118 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T1MSK (Timer 1 Interrupt Mask Register): C5H OVRMSK BTMMSK CMAMSK CMBMSK CMCMSK CAPMSK Initial value: 00H OVRMSK Control Overflow interrupt Overflow interrupt disable Overflow interrupt enable BTMMSK Control Timer Bottom interrupt Timer Bottom interrupt disable...
  • Page 119 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM PLLCR (PLL Control Register): 94H PLLCT7 PLLCT6 PLLCT5 PLLCT4 PLLCT3 PLLCT2 PLLCT1 PLLCT0 Initial value: 42H PLLCT[7:6] Pre Scaler (divider) Control PLLCT7 PLLCT6 description Div 1 Div 2 Div 4 Div 8 PLLCT5:[4] Feedback Control...

  • Page 120: Figure 49. Pll Frequency Flow Chart

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual FVCOIN Phase Pre Scaler Post Scaler FXIN FOUT Locked Loop PLLCT<7:6> fvco PLLCT<3:1> Feedback Divider PLLCT<5:4> Figure 49. PLL Frequency Flow Chart FVCOIN = 2MHz or 4MHz = FXIN / Pre-Divide FVCO = FVCOIN * Feedback-Divider = 104MHz or 128MHz (FVCO should be set below 200MHz)

  • Page 121: 8-Bit Timer/Event Counter 2, 3

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.2 8-bit timer/event counter 2, 3 Timer 2 and timer 3 can be used as either two 8-bit timer/counter or one 16-bit timer/counter. Each 8- bit timer/event counter consists of a multiplexer, a timer data register, a counter register, a mode register, an input capture register and a comparator.

  • Page 122: Table 17. Operating Modes Of Timer

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Table 17. Operating Modes of Timer 16BIT CAP2 CAP3 PWM3E T2CK[2:0] T3CK[1:0] T2/3_PE Timer 2 Timer 3 8-bit Timer 8-bit Timer 8-bit Event 8-bit Capture Counter 8-bit Capture 8-bit Compare Output 8-bit 10-bit PWM Timer/Counter...

  • Page 123: 8-Bit Timer/Counter Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.2.1 8-bit timer/counter mode 8-bit timer/counter mode is selected by control registers as shown in Figure 50. T2EN T2PE CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST ADDRESS: C6 T2CR INITIAL VALUE: 0000_0000 POL3 16BIT CAP3 T3CK1 T3CK0...

  • Page 124: Figure 51. Timer/Event Counter2, 3 Example

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual Match with T2DR/T3DR T2DR/T3DR Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 2, 3 (T2IF, T3IF) Interrupt Occur Occur Occur Interrupt Interrupt Interrupt Figure 51. Timer/Event Counter2, 3 Example T2DR/T3DR Value Disable Enable Clear&Start...

  • Page 125: 16-Bit Timer/Counter Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.2.2 16-bit timer/counter mode Timer register is being run with all 16 bits. A 16-bit timer/counter register T2, T3 are incremented from 0003H to FFFFH until it matches T2DR, T3DR and then resets to 0000H. The match output generates the Timer 2 interrupt (no timer 3 interrupt).

  • Page 126: Figure 54. 8-Bit Capture Mode For Timer2, 3

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual ADDRESS: C6 T2EN T2PE CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST T2CR INITIAL VALUE: 0000_0000 POL3 16BIT CAP3 T3CK1 T3CK0 T3CN T3ST ADDRESS: CA T3CR INITIAL VALUE: 0000_0000 T2ST T2CN ÷2 8-bit Timer2 Counter ÷4 Clear ÷16...

  • Page 127: Figure 55. Input Capture Mode Operation Of Timer 2, 3

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM CDR2, CDR3 Load T2/T3 Value Count Pulse Period Up-count TIME Ext. INT2,3 PIN Interrupt Request (INT2F,INT3F) Interrupt Interval Period Figure 55. Input Capture Mode Operation of Timer 2, 3 T2, T3 Interrupt Request (T2IF,T3IF) Ext. INT2,3 PIN...

  • Page 128: 16-Bit Capture Mode

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 11.2.4 16-bit capture mode 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The clock source is selected from T2CK[2:0] and T3CK[1:0] must set 11b and 16BIT bit must set to ‘1’.

  • Page 129: Pwm Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.2.5 PWM mode The timer 3 has a PWM (pulse Width Modulation) function. In PWM mode, the T3/PWM3 output pin outputs up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set T3_PE to ‘1’.

  • Page 130: Figure 58. Pwm Mode

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual POL3 16BIT CAP3 T3CK1 T3CK0 T3CN T3ST ADDRESS: CA T3CR INITIAL VALUE: 0000_0000 PW3H PW3H PW3H PW3H T3_PE ADDRESS: CD T3PWHR INITIAL VALUE: 0---_0000 Period High Duty High 8-bit Timer3 PWM Period Register T3PPR T3PHR[3:2]...

  • Page 131: 8-Bit (16-Bit) Compare Output Mode

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T3CR[1:0] = 10 (2us) T3PWHR = 00 T3PPR = 0E Write 0A to T3PPR T3PDR = 05 Source Clock T3/PWM POL = 1 Duty Cycle Duty Cycle Duty Cycle (1+05 )X2us = 12us (1+05 )X2us = 12us...

  • Page 132: Timer/Counter 2, 3 Register Description

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 11.2.8 Timer/counter 2, 3 register description Timer/Counter 2, 3 Register consists of Timer 2 Mode Control Register (T2CR), Timer 2 Register (T2), Timer 2 Data Register (T2DR), Capture 2 Data Register (CDR2), Timer 3 Mode Control Register (T3CR),...
  • Page 133 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T2 (Timer 2 Register: Read Case): C7H Initial value: 00H T2[7:0] T2 Counter data T2DR (Timer 2 Data Register: Write Case): C7H T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 Initial value: FFH T2D[7:0] T2 Compare data...
  • Page 134 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T3CR (Timer 3 Mode Count Register): CAH 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST Initial value: 00H Configure PWM polarity Negative (Duty Match: Clear) Positive (Duty Match: Set) 16BIT Select Timer 1 8/16-bit 8-bit 16-bit...
  • Page 135 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T3DR (Timer 3 Data Register: Write Case): CBH T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 Initial value: FFH T3D[7:0] T3 Compare data T3PPR (Timer 3 PWM Period Register: Write Case PWM mode only): CBH...
  • Page 136 11. Timer/PWM MC97FG316/MC97FG216 User’s manual T3PWHR (Timer 3 PWM High Register): CDH T3_PE PW3H3 PW3H2 PW3H1 PW3H0 Initial value: 00H T3_PE Control Timer 3 Output port operation NOTE: Only writable bit. Be careful Timer 3 Output disable Timer 3 Output enable...

  • Page 137: 16-Bit Timer 4

    MC97FG316/MC97FG216 User’s manual 11. Timer/PWM 11.3 16-bit timer 4 16-bit timer 4 consists of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, and Timer Mode Control Register. It is able to use internal 16-bit timer/ counter without a port output function.

  • Page 138: Timer 4 Register Description

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 11.3.3 Timer 4 register description The timer 4 register consists of Timer 4 Mode Control Register (T4CR), Timer 4 Low Register (T4L), Timer 4 Low Data Register (T4LDR), Low Capture 4 Data Register (LCDR4), Timer 4 High Register (T4H), Timer 4 High Data Register (T4HDR), High Capture 4 Data Register (HCDR4).
  • Page 139 MC97FG316/MC97FG216 User’s manual 11. Timer/PWM T4L (Timer 4 Low Register: Read Case): CFH T4L7 T4L6 T4L5 T4L4 T4L3 T4L2 T4L1 T4L0 Initial value: 00H T4L[7:0] T4L Counter T4LDR (Timer 4 Low Data Register: Write Case): CFH T4LD7 T4LD6 T4LD5 T4LD4...

  • Page 140: Timer Interrupt Status Register (Tmisr)

    11. Timer/PWM MC97FG316/MC97FG216 User’s manual 11.4 Timer interrupt status register (TMISR) TMISR (Timer Interrupt Status Register): AFH TMIF5 TMIF4 TMIF3 TMIF2 TMIF1 TMIF0 Initial value: 00H Timer 5 Interrupt Flag TMIF5 No Timer 5 interrupt Timer 5 interrupt occurred, write “1” to clear interrupt flag...

  • Page 141: Buzzer Driver

    MC97FG316/MC97FG216 User’s manual 12. Buzzer driver Buzzer driver The Buzzer consists of 6 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave is outputted through P12/BUZO pin. In buzzer data register BUZDR[5:0] controls the buzzer frequency and BUZDIV[1:0] selects fBUZ divided by DIV block. In buzzer control...

  • Page 142: Table 21. Buzzer Frequency At 1Mhz

    12. Buzzer driver MC97FG316/MC97FG216 User’s manual Table 21. Buzzer Frequency at 1MHz BUZDATA BUZDATA BUZDIV[1:0] BUZDIV[1:0] [5:0] [5:0] (fbuz/8) (fbuz/16) (fbuz/32) (fbuz/64) (fbuz/8) (fbuz/16) (fbuz/32) (fbuz/64) 62.500 31.250 15.625 7.813 1.894 0.947 0.473 0.237 31.250 15.625 7.813 3.906 1.838 0.919 0.460...

  • Page 143: Block Diagram

    MC97FG316/MC97FG216 User’s manual 12. Buzzer driver 12.1 Block diagram BUZEN fx/1 6-bit Up-Counter fx/2 Clear fx/4 Counter fx/8 fx/16 scaler Match fx/32 BUZO fx/64 Comparator fx/128 BUZOEN BUZDR BUCK[2:0] Figure 62. Buzzer Driver Block Diagram 12.2 Register map Table 22. Register Map...

  • Page 144: Buzzer Driver Register Description

    12. Buzzer driver MC97FG316/MC97FG216 User’s manual 12.3 Buzzer driver register description Buzzer Driver consists of Buzzer Data Register (BUZDR), Buzzer Control Register (BUZCR). BUZDR (Buzzer Data Register): 8FH BUZDIV1 BUZDIV2 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 Initial value: FFH BUZDIV[1:0]...

  • Page 145: 12-Bit Adc

    13. 12-bit ADC 12-bit ADC Analog-to-digital converter (ADC) of MC97FG316/MC97FG216 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has tenth analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 146: Block Diagram

    13. 12-bit ADC MC97FG316/MC97FG216 User’s manual 13.1 Block diagram ÷4 ÷8 SCLK ÷16 scaler ÷32 12bit A/D Converter Data Register ADCRH[7:0] ADCRL[7:4] ADST or CKSEL[1:0] ADCLK (8bit) (4bit) EXTRG VDD18C Clear AN14 AN13 AN12 Successive Approximation ADIF Interrupt Circuit Comparator...

  • Page 147: Figure 64. A/D Analog Input Pin Connecting Capacitor

    MC97FG316/MC97FG216 User’s manual 13. 12-bit ADC Analog AN0~ AN14 Input 0~1000pF Figure 64. A/D Analog Input Pin Connecting Capacitor Analog AVref Power Input 22uF Figure 65. Avref Pin Connecting Capacitor...

  • Page 148: Adc Operation

    13. 12-bit ADC MC97FG316/MC97FG216 User’s manual 13.2 ADC operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0 ADCRL7 ADCRL6 ADCRL5 ADCRL4 ADCRL[7:4] ADCRH[7:0] ADCRL[3:0] bits are “0”...

  • Page 149: Register Map

    MC97FG316/MC97FG216 User’s manual 13. 12-bit ADC 13.3 Register map Table 23. ADC Register Map Name Address Default Description ADCM A/D Converter Mode Register ADCRL A/D Converter Result High Register ADCRH A/D Converter Result Low Register ADCM2 A/D Converter Mode 2 Register 13.4...
  • Page 150 13. 12-bit ADC MC97FG316/MC97FG216 User’s manual ADCM (A/D Converter Mode Register): C0H STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 8FH STBY Control operation of A/D standby (power down) ADC module enable ADC module disable (power down) ADST Control A/D Conversion stop/start.
  • Page 151 MC97FG316/MC97FG216 User’s manual 13. 12-bit ADC ADCRH (A/D Converter Result High Register): C9H ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value: xxH ADDM[11:4] MSB align, A/D Converter High result (8-bit) ADDL[11:8] LSB align, A/D Converter High result (4-bit)
  • Page 152 13. 12-bit ADC MC97FG316/MC97FG216 User’s manual ADCM2 (A/D Converter Mode Register): C1H EXTRG TSEL2 TSEL1 TSEL0 AMUXEN ALIGN CKSEL1 CKSEL0 Initial value: 01H EXTRG A/D external Trigger External Trigger disable External Trigger enable TSEL[2:0] A/D Trigger Source selection TSEL2 TSEL1...

  • Page 153: Analog Comparator

    MC97FG316/MC97FG216 User’s manual 14. Analog comparator Analog comparator The Analog Comparator compares the input values on the positive pin AC+ and the negative pin AC-. When the voltage on the positive pin AC+ is higher than the voltage on the negative pin AC-, the Analog Comparator output, ACOUT, is set.

  • Page 154: Register Map

    14. Analog comparator MC97FG316/MC97FG216 User’s manual 14.3 Register map Table 24. Analog Comparator Register Map Name Address Direction Default Description ACCSR Analog Comparator Control & Status Register 14.4 Analog comparator register description Analog comparator register has one control register, Analog comparator control & status register (ACCSR).

  • Page 155: Usart

    15. USART USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART of MC97FG316/MC97FG216 features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 156: Block Diagram

    15. USART MC97FG316/MC97FG216 User’s manual 15.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD/ MISO Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) UPM0...

  • Page 157: Clock Generation

    MC97FG316/MC97FG216 User’s manual 15. USART 15.2 Clock generation Clock generation logic generates a base clock signal for Transmitter and Receiver. USART supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode and Slave Synchronous mode.

  • Page 158: External Clock (Xck)

    15. USART MC97FG316/MC97FG216 User’s manual 15.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 159: Data Format

    MC97FG316/MC97FG216 User’s manual 15. USART 15.5 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART supports all 30 combinations of the following as valid frame formats.

  • Page 160: Parity Bit

    15. USART MC97FG316/MC97FG216 User’s manual 15.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. Parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 161: Parity Generator

    MC97FG316/MC97FG216 User’s manual 15. USART UDRE flag indicates whether the transmit buffer is ready to be loaded with new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains transmit data which has not yet been moved into the shift register.

  • Page 162: Usart Receiver

    15. USART MC97FG316/MC97FG216 User’s manual 15.8 USART receiver USART Receiver is enabled by setting the RXE bit in the UCTRLx1 register. When the Receiver is enabled, normal pin operation of the RXD pin is overridden by the USART as the serial input pin of the Receiver.

  • Page 163: Parity Checker

    MC97FG316/MC97FG216 User’s manual 15. USART Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is set when the stop bit was correctly detected as “1”, and the FE flag is cleared when the stop bit was incorrect, i.e. detected as “0”.

  • Page 164: Figure 73. Start Bit Sampling

    15. USART MC97FG316/MC97FG216 User’s manual Figure 73 describes sampling process of the start bit of an incoming frame. The sampling rate is 16 times the baud-rate for normal mode, and 8 times the baud rate for Double Speed mode (U2X=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process.

  • Page 165: Figure 74. Sampling Of Data And Parity Bit

    MC97FG316/MC97FG216 User’s manual 15. USART BIT n Sample (U2X = 0) Sample (U2X = 1) Figure 74. Sampling of Data and Parity Bit A process for detecting stop bit is similar to the clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected.

  • Page 166: Spi Mode

    15. USART MC97FG316/MC97FG216 User’s manual 15.9 SPI mode USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer  Master or Slave operation  Supports all four SPI modes of operation (mode0, 1, 2, and 3) ...

  • Page 167: Figure 76. Spi Clock Formats When Ucpha=0

    MC97FG316/MC97FG216 User’s manual 15. USART (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 76. SPI Clock Formats when UCPHA=0 When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.

  • Page 168: Figure 77. Spi Clock Formats When Ucpha=1

    15. USART MC97FG316/MC97FG216 User’s manual (UCPOL=0 (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 77. SPI Clock Formats when UCPHA=1 When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first XCK edge.

  • Page 169: 15.10 Register Map

    MC97FG316/MC97FG216 User’s manual 15. USART 15.10 Register map Table 27. SPI Register Map Name Address Default Description UCTRL01 USART Control 1 Register 0 UCTRL02 USART Control 2 Register 0 UCTRL03 USART Control 3 Register 0 USTAT0 USART Status Register 0...

  • Page 170: 15.11 Usart Register Description

    15. USART MC97FG316/MC97FG216 User’s manual 15.11 USART register description USART module consists of USART Control 1 Register (UCTRLx1), USART Control 2 Register (UCTRLx2), USART Control 3 Register (UCTRLx3), USART Status Register (USTATx), USART Data Register (UDATAx), and USART Baud Rate Generation Register (UBAUDx).
  • Page 171 MC97FG316/MC97FG216 User’s manual 15. USART And Sample means detecting of incoming receive bit, Setup means preparing transmit data. UCPOL UCPHA Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising)
  • Page 172 15. USART MC97FG316/MC97FG216 User’s manual UCTRLx2 (USART Control 2 Register) E3H, FBH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 173 MC97FG316/MC97FG216 User’s manual 15. USART UCTRLx3 (USART Control 3 Register) E4H, FCH MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 174 15. USART MC97FG316/MC97FG216 User’s manual USTATx (USART Status Register) E5H UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 175 MC97FG316/MC97FG216 User’s manual 15. USART UBAUDx (USART Baud-Rate Generation Register) E6H, FEH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.

  • Page 176: Baud Rate Setting (Example)

    15. USART MC97FG316/MC97FG216 User’s manual 15.12 Baud rate setting (example) Table 28. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies Baud fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR...

  • Page 177: Spi

    MC97FG316/MC97FG216 User’s manual 16. SPI There is Serial Peripheral Interface (SPI) one channel in MC97FG316. The SPI allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI, MISO, SCK, SS), support Master/Slave mode, can select serial clock (SCK) polarity, phase and whether LSB first data transfer or MSB first data transfer.

  • Page 178: Data Transmit/ Receive Operation

    16. SPI MC97FG316/MC97FG216 User’s manual 16.2 Data transmit/ receive operation User can use SPI for serial data communication by following step Select SPI operation mode (master/slave, polarity, phase) by control register SPICR. When the SPI is configured as a Master, it selects a Slave by SS signal (active low). When the SPI is configured as a Slave, it is selected by SS signal incoming from Master When the user writes a byte to the data register SPIDR, SPI will start an operation.

  • Page 179: Timing Waveform

    MC97FG316/MC97FG216 User’s manual 16. SPI 16.4 Timing waveform (CPOL=0) (CPOL=1) MISO/MOSI (Output) MOSI/MISO (Input) TCIR SS_HIGH Figure 79. SPI Transmit/Receive Timing Diagram at CPHA = 0 (CPOL=0) (CPOL=1) MISO/MOSI (Output) MOSI/MISO (Input) TCIR SS_HIGH Figure 80. SPI Transmit/Receive Timing Diagram at CPHA = 1 16.5...

  • Page 180: Spi Register Description

    16. SPI MC97FG316/MC97FG216 User’s manual 16.6 SPI register description The SPI Register consists of SPI Control Register (SPICR), SPI Status Register (SPISR) and SPI Data Register (SPIDR) SPICR (SPI Control Register): D2H SPIEN FLSB CPOL CPHA DSCR SCR1 SCR0 Initial value: 00H...
  • Page 181 MC97FG316/MC97FG216 User’s manual 16. SPI SPIDR (SPI Data Register): D3H SPIDR7 SPIDR6 SPIDR5 SPIDR4 SPIDR3 SPIDR2 SPIDR1 SPIDR0 Initial value: 00H SPIDR [7:0] SPI data register. Although you only use reception, user must write any data in here to start the SPI operation.

  • Page 182: I2C

    17. I2C MC97FG316/MC97FG216 User’s manual The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.

  • Page 183: I2C Bit Transfer

    MC97FG316/MC97FG216 User’s manual 17. I2C 17.2 I2C bit transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 184: Data Transfer

    17. I2C MC97FG316/MC97FG216 User’s manual 17.4 Data transfer Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 185: Acknowledge

    MC97FG316/MC97FG216 User’s manual 17. I2C 17.5 Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

  • Page 186: Synchronization/ Arbitration

    17. I2C MC97FG316/MC97FG216 User’s manual 17.6 Synchronization/ arbitration Clock synchronization is performed by using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.

  • Page 187: Operation

    MC97FG316/MC97FG216 User’s manual 17. I2C 17.7 Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to execute other operations during an I2C byte transfer.
  • Page 188 17. I2C MC97FG316/MC97FG216 User’s manual To operate as a slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section).

  • Page 189: Master Receiver

    MC97FG316/MC97FG216 User’s manual 17. I2C After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘1’...
  • Page 190 17. I2C MC97FG316/MC97FG216 User’s manual I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can prepare and transmit more data to master. Configure ACKEN bit in I2CMR to decide whether I2C ACKnowledges the next data to be received or not.

  • Page 191: Slave Transmitter

    MC97FG316/MC97FG216 User’s manual 17. I2C 17.7.3 Slave transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 192: Slave Receiver

    17. I2C MC97FG316/MC97FG216 User’s manual 17.7.4 Slave receiver To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 193: Register Map

    MC97FG316/MC97FG216 User’s manual 17. I2C 17.8 Register map Table 30. I2C Register Map Name Address Default Description I2CMR I2C Mode Control Register I2CSR I2C Status Register I2CSCLLR SCL Low Period Register I2CSCLHR SCL High Period Register I2CSDAHR SDA Hold Time Register...

  • Page 194: I2C Register Description

    17. I2C MC97FG316/MC97FG216 User’s manual 17.9 I2C register description I2C Registers are composed of I2C Mode Control Register (I2CMR), I2C Status Register (I2CSR), SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time Register (I2CSDAHR), I2C Data Register (I2CDR), and I2C Slave Address Register (I2CSAR).
  • Page 195 MC97FG316/MC97FG216 User’s manual 17. I2C I2CSR (I2C Status Register): DBH GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value: 00H GCALL This bit has different meaning depending on whether I2C is master or slave. NOTE: When I2C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 196 17. I2C MC97FG316/MC97FG216 User’s manual I2CSCLLR (SCL Low Period Register): DCH SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value: 3FH SCLL[7:0] This register defines the LOW period of SCL when I2C operates in master mode. The base clock is SCLK, the system clock, and the period ×...
  • Page 197 MC97FG316/MC97FG216 User’s manual 17. I2C I2CSAR (I2C Slave Address Register): D7H SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN Initial value: 00H SLA[7:1] These bits configure the slave address of this I2C module when I2C operates in slave mode. GCALLEN This bit decides whether I2C allows general call address or not when I2C operates in slave mode.

  • Page 198: Power Down Operation

    MC97FG316/MC97FG216 User’s manual Power down operation MC97FG316/MC97FG216 has three power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. MC97FG316/MC97FG216 provides three kinds of power saving functions, IDLE, STOP1 and STOP2 mode. In three modes,...

  • Page 199: Peripheral Operation In Idle/Stop Mode

    MC97FG316/MC97FG216 User’s manual 18. Power down operation 18.1 Peripheral operation in IDLE/STOP mode Table 31. Peripheral Operation during Power down Mode Peripheral IDLE mode STOP1 mode STOP2 mode ALL CPU Operation are ALL CPU Operation are ALL CPU Operation are...

  • Page 200: Idle Mode

    18. Power down operation MC97FG316/MC97FG216 User’s manual 18.2 IDLE mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.

  • Page 201: Stop Mode

    MC97FG316/MC97FG216 User’s manual 18. Power down operation 18.3 STOP mode The power control register is set to ‘03h’ to enter the STOP Mode. In the stop mode, the main oscillator, system clock and peripheral clock is stopped, but watch timer continue to operate. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.

  • Page 202: Figure 91. Stop Mode Release Timing By /Reset

    18. Power down operation MC97FG316/MC97FG216 User’s manual CPU Clock RESETB Release STOP Command BIT Counter Clear & Start 64 T TST = 65.5ms @ 16MHz Normal Operation STOP Mode Normal Operation �� = 1/f ������ = × ������ �������� ÷ ��������...

  • Page 203: Release Operation Of Stop1, 2 Mode

    MC97FG316/MC97FG216 User’s manual 18. Power down operation 18.4 Release operation of STOP1, 2 mode After STOP1, 2 mode is released, the operation begins according to content of related interrupt register just before STOP1, 2 modes start (Figure 92). Interrupt Enable Flag of All (EA) of IE should be set to `1`.

  • Page 204: Register Map

    18. Power down operation MC97FG316/MC97FG216 User’s manual 18.5 Register map Table 32. Power down Operation Register Map Name Address Direction Default Description PCON Power Control Register 18.6 Power down operation register description The power down operation register consists of the power control register (PCON).

  • Page 205: Reset

    MC97FG316/MC97FG216 User’s manual 19. Reset Reset MC97FG316 has reset by external RESETB pin. The following is the hardware setting value. Table 33. Reset State On chip hardware Initial value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register...

  • Page 206: Reset Noise Canceller

    19. Reset MC97FG316/MC97FG216 User’s manual 19.2 Reset noise canceller Figure 94 is a Noise canceller diagram for Noise cancel of RESET. It has the Noise cancel value of about 7us (@VDD=5V) to the low input of System Reset. t < T t <...

  • Page 207: Figure 96. Internal Reset Release Timing On Power-Up

    MC97FG316/MC97FG216 User’s manual 19. Reset Fast VDD Rise Time nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETb Oscillation Figure 96. Internal RESET Release Timing On Power-Up Counting for configure option read start after POR is released Internal nPOR PAD RESETB “H”...

  • Page 208: Figure 98. Boot Process Waveform

    19. Reset MC97FG316/MC97FG216 User’s manual Figure 98. Boot Process Waveform Table 34. Boot Process Description Process Description Remarks No Operation ②  1 POR level Detection about 1.4V ~ 1.5V  RING OSC (12kHz) ON ③  (RING-OSC12kHz/32) × 30h...

  • Page 209: External Resetb Input

    MC97FG316/MC97FG216 User’s manual 19. Reset 19.4 External resetb input External RESETB is input to a Schmitt trigger. A reset is accomplished by holding the reset pin low for at least 7us over, within the operating voltage range and oscillation stable status, it is applied, and the internal state is initialized.

  • Page 210: Low Voltage Reset Processor

    19.5 Low voltage reset processor MC97FG316/MC97FG216 has an On-chip Brown-out detection circuit for monitoring the VDD level by comparing it to a fixed trigger level. The trigger level for the LVR can be selected by LVRLS[1:0] bit to be 1.6V, 2.5V, 3.6V or 4.2V. In the STOP mode, this will contribute significantly to the total current consumption.

  • Page 211: Register Map

    MC97FG316/MC97FG216 User’s manual 19. Reset “H” “H” Internal nPOR “H” PAD RESETB (R20) LVR_RESETB .. 2F 30 00 01 02 BIT (for Config) 3F 40 00 01 02 03 01 02 BIT (for Reset) 256us X 30h = about 12ms...

  • Page 212: Reset Operation Register Description

    19. Reset MC97FG316/MC97FG216 User’s manual 19.7 Reset operation register description Reset control register consists of the LVR Control Register (LVRCR). LVRCR (LVR Control Register): 86H PORF EXTRF WDTRF OCDRF LVRRF LVRLS[1] LVRLS[0] LVREN Initial value: 81H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.

  • Page 213: Memory Programming

    20. Memory programming Memory programming MC97FG316 incorporates flash and data EEPROM memory to which a program can be written, erased, and overwritten while mounted on the board. Also, data EEPROM can be programmed or erased in user program. Flash area can be programmed in only OCD II or parallel ROM mode.

  • Page 214: Register Description For Flash And Eeprom

    20. Memory programming MC97FG316/MC97FG216 User’s manual 20.1.2 Register description for Flash and EEPROM FEMR (Flash Mode Register): EAH FSEL ESEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory ESEL Select data EEPROM...
  • Page 215 MC97FG316/MC97FG216 User’s manual 20. Memory programming FECR (Flash and EEPROM Control Register): EBH EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory...
  • Page 216 20. Memory programming MC97FG316/MC97FG216 User’s manual FESR (Flash and EEPROM Status Register): ECH PEVBSY VFYGOOD PCRCRD ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification...
  • Page 217 MC97FG316/MC97FG216 User’s manual 20. Memory programming FEARH (Flash and EEPROM address high Register): F4H ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1 ARH0 Initial value: 00H ARH[7:0] Flash and EEPROM address high FEAR registers are used for program, erase and auto-verify. In program and erase mode, it is page address and ignored the same least significant bits as the number of bits of page address.

  • Page 218: Table 37. Program/Erase Time

    20. Memory programming MC97FG316/MC97FG216 User’s manual FETCR (Flash and EEPROM Time control Register): EDH TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash and EEPROM Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter. It increases by one at each divided system clock frequency (=SCLK/128).

  • Page 219: Memory Map

    MC97FG316/MC97FG216 User’s manual 20. Memory programming 20.2 Memory map 20.2.1 Flash memory map Program memory uses 16-Kbyte of Flash memory. It is read by byte and written by byte or page. One page is 32-byte FFFFh pgm/ers/vfy Flash 3FFFh 16KBytes 0000h Figure 104.

  • Page 220: Data Eeprom Memory Map

    20. Memory programming MC97FG316/MC97FG216 User’s manual 20.2.2 Data EEPROM memory map Data EEPROM memory uses 512-byte of EEPROM. It is read by byte and written by byte or page. One page is 16-byte. It is mapped to external data memory of 8051...

  • Page 221: Serial In-System Program Mode

    MC97FG316/MC97FG216 User’s manual 20. Memory programming 20.3 Serial in-system program mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger. 20.3.1 Flash operation Configuration (This Configuration is just used for follow description) FEMR[4] &...

  • Page 222: Figure 109. Sequence Of Bulk Erase Of Flash Memory

    20. Memory programming MC97FG316/MC97FG216 User’s manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency(500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 109. Sequence of Bulk Erase of Flash Memory Flash Read Step 1.
  • Page 223 MC97FG316/MC97FG216 User’s manual 20. Memory programming Enable program mode Step 1. Enter OCD (=ISP) mode NOTE1 Step 2. Set ENBDM bit of BCR. Step 3. Enable debug and Request debug mode. Step 4. Enter program/erase mode sequence NOTE2 (1) Write 0xAA to 0xF555.
  • Page 224 20. Memory programming MC97FG316/MC97FG216 User’s manual Flash page erase mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:1000_1001 Step 4. Write ‘h00 to page buffer. (Data value is not important.) Step 5.
  • Page 225 MC97FG316/MC97FG216 User’s manual 20. Memory programming Flash OTP area read mode Step 1. Enter OCD(=ISP) mode. Step 2. Set ENBDM bit of BCR. Step 3. Enable debug and Request debug mode. Step 4. Select OTP area. FEMR:1000_0101 Step 5. Read data from Flash.
  • Page 226 20. Memory programming MC97FG316/MC97FG216 User’s manual Flash OTP area erase mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:1000_1001 Step 4. Write ‘h00 to page buffer. (Data value is not important.) Step 5.

  • Page 227: Data Eeprom Operation

    MC97FG316/MC97FG216 User’s manual 20. Memory programming Flash page buffer read Step 1. Enable program mode. Step 2. Select page buffer. FEMR:1000_1001 Step 3. Read data from Flash. 20.3.2 Data EEPROM operation Program and erase operation of Data EEPROM are executed by direct and indirect address mode.
  • Page 228 20. Memory programming MC97FG316/MC97FG216 User’s manual EEPROM write mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 0100_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:0100_1001 Step 4. Write data to page buffer.(Address automatically increases by twin.) Step 5.
  • Page 229 MC97FG316/MC97FG216 User’s manual 20. Memory programming EEPROM bulk erase mode Step 1. Enable program mode. Step 2. Reset page buffer. FEMR: 0100_0001 FECR:0000_0010 Step 3. Select page buffer. FEMR:0100_1001 Step 4. Write ‘h00 to page buffer. (Data value is not important.) Step 5.

  • Page 230: Summary Of Flash And Data Eeprom Program/Erase Mode

    20. Memory programming MC97FG316/MC97FG216 User’s manual 20.3.3 Summary of flash and data EEPROM program/erase mode Table 38. Operation Mode Operation mode Description Flash read Read cell by byte. Flash write Write cell by bytes or page. Flash page erase Erase cell by page.

  • Page 231: Mode Entrance Method Of Isp And Byte-Parallel Mode

    20.5 Security MC97FG316 provides Lock bits which can be left unprogrammed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 39. The Lock bits can be erased to “0” with only the bulk erase command and a value of more than 0x80 at FETCR.

  • Page 232: Configure Option

    20. Memory programming MC97FG316/MC97FG216 User’s manual 20.6 Configure option For the configure option control, corresponding data should be written in the configure option area by programmer (writer tools). Also, the value of configure option can be read at address 0x4000.

  • Page 233: How To Write The Configure Option In User Program

    MC97FG316/MC97FG216 User’s manual 20. Memory programming 20.6.1 How to write the configure option in user program To reapply the configure value to be written by programmer (writer tool) #define coderom ((unsigned char volatile code *) 0) #define FUSE_CONF *(volatile unsigned char xdata *) 0x2F50 void main(void) FUSE_CONF=coderom[0x4000];...

  • Page 234: Electrical Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual Electrical characteristics 21.1 Absolute maximum ratings Table 40. Absolute Maximum Ratings Parameter Symbol Rating Unit Remark Supply voltage -0.3~+6.5 – Normal voltage pin Voltage on any pin with respect to VSS 0.3~VDD+0.3 0.3~VDD+0.3 Maximum current output sourced by (I per I/O pin) ∑I...

  • Page 235: A/D Converter Characteristics

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.3 A/D converter characteristics Table 42. A/D Converter Characteristics (TA=-40C ~ +85C or T =-40C ~ +105C, VDD=AVDD=2.7V ~ 5.5V, VSS=0V) Parameter Symbol Condition Unit converting bits Resolution Integral non-linearity Vref=5.12V, ±3 Vss=0V, TA=+25℃...

  • Page 236: Power-On Reset Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual 21.5 Power-on reset characteristics Table 44. Power-On Reset Characteristics =-40°C ~ +85°C or T =-40C ~ +105C, VDD=1.8 ~ 5.5V, VSS=0V) Parameter Symbol Condition Unit RESET release level RESET release level 0.05 V/ms POR current 21.6...

  • Page 237: Ring-Oscillator Characteristics

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.8 Ring-oscillator characteristics Table 47. Ring-Oscillator Characteristics =-40°C ~ +85°C or T =-40C ~ +105C, VDD=1.8 ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Frequency = 1.8 ~ 5.5V RING Tolerance = -40°C to +85°C With 0.1uF...

  • Page 238: 21.10 Dc Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual 21.10 DC characteristics Table 49. DC Characteristics (VDD =2.7~5.5V, VSS =0V, INTOSC=16.0MHz, T =-40~+85C or T =-40C ~ +105C) Parameter Symbol Condition Unit Input low voltage P2[2] -0.5 0.2VDD All others PAD -0.5 0.2VDD...

  • Page 239: 21.11 Ac Characteristics

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.11 AC characteristics Table 50. AC Characteristics = -40°C ~ +85°C or T =-40C ~ +105C, VDD= 1.8V – 5.5V) Parameter Symbol Conditions Unit RESETB input low width Input, VDD=5V – Interrupt input high, low All interrupt, VDD=5V –...

  • Page 240: 21.12 Spi Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual 21.12 SPI characteristics Table 51. SPI Characteristics = -40°C – +85°C or T =-40C ~ +105C, VDD= 1.8V – 5.5V) Parameter Symbol Conditions Unit Output clock pulse period Internal SCK source – Input clock pulse period External SCK source –...

  • Page 241: 21.13 I2C Characteristics

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.13 I2C characteristics Table 52. I2C Characteristics = -40°C – +85°C or T =-40C ~ +105C, VDD= 1.8V – 5.5V) Parameter Symbol Standard mode High-speed mode Unit Clock frequency Clock high pulse width –...

  • Page 242: 21.14 Main Clock Oscillator Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual 21.14 Main clock oscillator characteristics Table 53. Main Clock Oscillator Characteristics (VDD=5.0V±10%, VSS=0V, T =-40~+85℃ or T =-40C ~ +105C) Parameter Operating Voltage (VDDEXT) 1.5V 5.5V TEMP -40℃ 85℃ 660uA @4Mhz, VDDEXT(5V) Operating Frequency 16Mhz Ext.

  • Page 243: 21.16 Operating Voltage Range

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.16 Operating voltage range =4.0 to 16MHz): Crystal =32 to 38kHz) =1, 4, 8, 16MHz): Internal OSC 16.0MHz 32.768kHz 4.0MHz 1.0MHz Supply voltage (V) Supply voltage (V) Figure 116. Operating Voltage Range...

  • Page 244: 21.17 Typical Characteristics

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual 21.17 Typical characteristics These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g.

  • Page 245: Figure 118. Vol Vs Iol

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics Figure 118. VOL vs IOL Figure 119. Power Supply Current (RUN, IDLE )

  • Page 246: Figure 120. Stop1 Current

    21. Electrical characteristics MC97FG316/MC97FG216 User’s manual Figure 120. Stop1 Current Figure 121. Stop2 Current...

  • Page 247: 21.18 Recommended Circuit And Layout

    MC97FG316/MC97FG216 User’s manual 21. Electrical characteristics 21.18 Recommended circuit and layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS)

  • Page 248: Package Information

    22. Package information MC97FG316/MC97FG216 User’s manual Package information This chapter provides MC97FG316/MC97FG216 package information. 22.1 32 LQFP package information Figure 123. 32 LQFP Package Outline...

  • Page 249: 32 Qfn Package Information

    MC97FG316/MC97FG216 User’s manual 22. Package information 22.2 32 QFN package information Figure 124. 32 QFP Package Outline...

  • Page 250: 28 Tssop Package Information

    22. Package information MC97FG316/MC97FG216 User’s manual 22.3 28 TSSOP package information Figure 125. 28 TSSOP Package Outline...

  • Page 251: Tssop Package Information

    MC97FG316/MC97FG216 User’s manual 22. Package information 22.4 20 TSSOP package information Figure 126. 20 TSSOP Package Outline...

  • Page 252: Ordering Information

    23. Ordering information MC97FG316/MC97FG216 User’s manual Ordering information Table 55. MC97FG316/MC97FG216 Device Ordering Information Device name Flash XRAM/ EEPROM I/O port Package Temperature input MC97FG316L 32LQFP -40~+85C MC97FG316U bytes / 256 bytes 32QFN bytes MC97FG316R 28TSSOP MC97FG216R 20TSSOP MC97FG316LB2* 32LQFP -40~+105C...

  • Page 253: Development Tools

    ABOV semiconductor does not provide any compiler for MC97FG316/MC97FG216. It is recommended to consult a compiler provider. Since MC97FG316/MC97FG216 has Mentor 8051 as its core, and ROM is smaller than 32Kbytes in size, a developer can use any standard 8051 compiler of other providers.

  • Page 254: Programmers

    MC97FG316/MC97FG216 User’s manual 24.3 Programmers 24.3.1 E-PGM+ E-PGM+ USB is a single programmer. A user can program MC97FG316/MC97FG216 directly using the E-PGM+. Figure 129. E-PGM+ (Single Writer) and Pinouts 24.3.2 OCD II emulator OCD II emulator allows a user to write code on the device too, since OCD II debugger supports ISP (In System Programming).

  • Page 255: Flash Programming

    24.4 Flash programming Program memory of MC97FG316/MC97FG216 is a flash type. This flash ROM is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. For more information about flash memory programming, please refer to 20. Memory programming.

  • Page 256: Figure 131. Pcb Design Guide For On-Board Programming

    24. Development tools MC97FG316/MC97FG216 User’s manual E-PGM+ , E-GANG4 , E-GANG6 R1 (2k ~ 5k ) DSCL(I) To application circuit R2 (2k ~ 5k ) DSDA(I/O) To application circuit NOTES: In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA.

  • Page 257: On-Chip Debug System

    24. Development tools 24.5 On-chip debug system MC97FG316/MC97FG216 supports On-chip debug II(OCD II) system. We recommend to develop and debug program with MC97FG316/MC97FG216. On-chip debug system of MC97FG316/MC97FG216 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD II interface can be found in this section.

  • Page 258: Two-Pin External Interface

    24. Development tools MC97FG316/MC97FG216 User’s manual Figure 132 shows a block diagram of the OCD II interface and the On-chip Debug system. Figure 132. On-Chip Debugging System in Block Diagram 24.5.1 Two-pin external interface Basic transmission packet 10-bit packet transmission using two-pin interface.

  • Page 259: Figure 133. 10-Bit Transmission Packet

    MC97FG316/MC97FG216 User’s manual 24. Development tools Figure 133. 10-bit Transmission Packet Packet transmission timing Figure 134. Data Transfer on Twin Bus...

  • Page 260: Figure 135. Bit Transfer On Serial Bus

    24. Development tools MC97FG316/MC97FG216 User’s manual Figure 135. Bit Transfer on Serial Bus Figure 136. Start and Stop Condition Figure 137. Acknowledge on Serial Bus...

  • Page 261: Figure 138. Clock Synchronization During Wait Procedure

    MC97FG316/MC97FG216 User’s manual 24. Development tools Figure 138. Clock Synchronization during Wait Procedure Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). Figure 139. Connection of Transmission...

  • Page 262: Appendix

    Appendix MC97FG316/MC97FG216 User’s manual Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.

  • Page 263: Table 59. Instruction Table: Logical

    MC97FG316/MC97FG216 User’s manual Appendix Table 59. Instruction Table: Logical Logical Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...

  • Page 264: Table 60. Instruction Table: Data Transfer

    Appendix MC97FG316/MC97FG216 User’s manual Table 60. Instruction Table: Data Transfer Data transfer Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7...

  • Page 265: Table 61. Instruction Table: Boolean

    MC97FG316/MC97FG216 User’s manual Appendix Table 61. Instruction Table: Boolean Boolean Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...

  • Page 266: Table 62. Instruction Table: Branching

    Appendix MC97FG316/MC97FG216 User’s manual Table 62. Instruction Table: Branching Branching Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...

  • Page 267: Table 63. Instruction Table: Miscellaneous

    MC97FG316/MC97FG216 User’s manual Appendix Table 63. Instruction Table: Miscellaneous Miscellaneous Mnemonic Description Bytes Cycles Hex code No operation Additional instructions (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP...

  • Page 268: Revision History

    Revision history MC97FG316/MC97FG216 User’s manual Revision history Date Revision Description 2015.06.05 1.00 First creation 2015.08.12 1.01 Added 32QFN 2015.08.18 1.02 Updated 28TSSOP device name and Analog Comparator description 2015.10.29 1.03 Added the description for using external reset. Add E-PGM+(single writer) in Chapter 24.3 Programmers Changed to ‘-10mA/-80mA for IOH &...
  • Page 269 Renewed the contents of a manual including text format, description and so on Expanded operating temperature 105C electrical characteristics Added how to write the configure option in user program 2020.07.20 1.12 Corrected EEPROM size at Table 1. MC97FG316/MC97FG216 Device Features and Peripheral Counts.

  • Page 270: Important Notice

    ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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