Analog Devices ADSP-21479 EZ-Board Manual page 39

The shift register's signals can be configured as follows.
• The
SR_SCLK
PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin
(
SR_SCLK
• The
SR_LAT
PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated
pin (
SR_LAT
• The
SR_SDI
any of the DAI pins (1–8), and one dedicated pin (
Note that the
SR_SCLK
same source, except in case of where
and
SR_SCLK SR_LAT
If comes from PCGA/B, then
SR_SCLK
signals. If
SR_SDI
generate
SR_SDI
Access to the shift register of the processor is available via the shift register
interface connector (
they require off-board capabilities. For more information, see
ister Interface Connector (P4)" on page
ADSP-21479 EZ-Board Evaluation System Manual
can come from any of the
).
can come from any of
).
input can from any of
, , and
SR_LAT
come from PCGA/B.
and
SR_SCLK SR_LAT
signal.
). Users can use a standard 2 mm ribbon cable if
P4
Using The ADSP-21479 EZ-Board
SPORT0–7 SCLK
frame sync outputs,
SPORT0–7
serial data outputs,
SPORT0–7
inputs must come from the
SR_SDI
comes from PCGA/B or
SR_SCLK
generate
SPORT0–7
come from PCGA/B, then
2-27.
outputs,
).
SR_SDI
and
SR_LAT
SPORT0–7
"Shift Reg-
1-19