Flash Wp Jumper (Jp1); S/Pdif Loopback Jumper (Jp2); Uart Rts/Cts Jumper (Jp3); Uart Loopback Jumper (Jp4) - Analog Devices ADSP-21479 EZ-Board Manual

Jumpers

Flash WP Jumper (JP1)

The flash WP jumper (
chip. Block 0 is located at address range
POST begins at block 0 and continues on to other blocks in flash mem-
ory. When the jumper is installed on
from Analog Devices is used, block 0 is read-only. By default,
installed.

S/PDIF Loopback Jumper (JP2)

The S/PDIF loop back jumper (
jumper loops back any digital audio signal from the S/PDIF's
pin to the S/PDIF's

UART RTS/CTS Jumper (JP3)

The UART RTS/CTS jumper (
RS-232 interface. By default,

UART Loopback Jumper (JP4)

The UART loop back jumper (
jumper loops back UART receive data from UART transmit data. By
default, is not installed.
JP4

DSP Audio Oscillator Jumper (JP5)

The processor audio oscillator jumper (
oscillator to the
make the processor the master and the AD1939 device—the slave. By
default, is not installed, resulting in the AD1939 being the master,
JP5
and the processor being the slave.
2-20
) write-protects block 0 of the parallel flash
JP1
JP2
pin. By default,
Data In
JP3
is installed.
JP3
JP4
pin of the processor. The jumper can be used to
DAI_P17
ADSP-21479 EZ-Board Evaluation System Manual
0x0400 0000–0x0400 1FFF
, and the parallel flash driver
JP1
) is used for internal testing only. The
is not installed.
JP2
) connects the
RTS
) is used for internal testing only. The
connects a 24.576 MHz
JP5)
. The
is not
JP1
Data Out
and pins of the
CTS