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Standard Event Status register
The Standard Event Status Register monitors the fol-
lowing instrument status events:
• OPC - Operation Complete
• RQC - Request Control
• QYE - Query Error
• DDE - Device Dependent Error
• EXE - Execution Error
• CME - Command Error
• URQ - User Request
• PON - Power On
When one of these events occur, the event sets the cor-
responding bit in the register. If the bits are enabled in
the Standard Event Status Enable Register, the bits set
in this register generate a summary bit to set bit 5
(ESB) in the Status Byte Register.
The contents of the Standard Event Status Register can
be read and the register cleared by sending the *ESR?
query. The value returned is the total bit weights of all
of the bits that are set at the present time.
Enabling register bits with masks
Several masks are available which you can use to enable
or disable individual bits in each register. For example,
you can disable the Hardcopy bit in the OPERation Sta-
tus Register so that even though it goes high, it can
never set the summary bit in the status byte high.
Use the *SRE common command to set or query the
mask for the Status Byte Register.
The masks for the OPERation Status and QUEStionable
Status registers are set and queried using the STATus
subsystem's ENABle commands.
Use the *ESE common command to set or query the
mask for the Standard Event Status Register.
The *CLS common command clears all event registers
and all queues except the output queue. If *CLS is sent
immediately following a program message terminator,
the output queue is also cleared. In addition, the
request for the *OPC bit is also cleared.
For example, suppose your application requires an
interrupt whenever any type of error occurs. The error
related bits in the Standard Event Status Register are
bits 2 through 5. The sum of the decimal weights of
Monitoring the Instrument 4-19
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