Xilinx Virtex-7 VC7222 User Manual page 56

Fpga gth and gtz transceiver characterization board
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Appendix C: Master Constraints File Listing
56
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set_property IOSTANDARD
set_property PACKAGE_PIN AM26
set_property IOSTANDARD
set_property PACKAGE_PIN AN26
set_property IOSTANDARD
set_property PACKAGE_PIN AP26
set_property IOSTANDARD
set_property PACKAGE_PIN AM24
set_property IOSTANDARD
set_property PACKAGE_PIN AN24
set_property IOSTANDARD
#IIC
set_property PACKAGE_PIN AF24
set_property IOSTANDARD
set_property PACKAGE_PIN AG24
set_property IOSTANDARD
#PMBUS
set_property PACKAGE_PIN AE25
set_property IOSTANDARD
set_property PACKAGE_PIN AF25
set_property IOSTANDARD
set_property PACKAGE_PIN AH23
set_property IOSTANDARD
set_property PACKAGE_PIN AJ23
set_property IOSTANDARD
#USB_GPIOs
set_property PACKAGE_PIN AD10
set_property IOSTANDARD
set_property PACKAGE_PIN AC8
set_property IOSTANDARD
set_property PACKAGE_PIN AD8
set_property IOSTANDARD
set_property PACKAGE_PIN AK11
set_property IOSTANDARD
#UART
set_property PACKAGE_PIN AK10
set_property IOSTANDARD
set_property PACKAGE_PIN AL10
set_property IOSTANDARD
set_property PACKAGE_PIN AL9
set_property IOSTANDARD
set_property PACKAGE_PIN AG11
set_property IOSTANDARD
#SYSTEMACE
set_property PACKAGE_PIN AE11
set_property IOSTANDARD
set_property PACKAGE_PIN AE10
set_property IOSTANDARD
set_property PACKAGE_PIN AF10
set_property IOSTANDARD
set_property PACKAGE_PIN AG10
set_property IOSTANDARD
set_property PACKAGE_PIN AH11
set_property IOSTANDARD
set_property PACKAGE_PIN AE12
set_property IOSTANDARD
#SPI - MGT PWR MODULE
set_property PACKAGE_PIN AC12
set_property IOSTANDARD
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LVCMOS18 [get_ports APP_LED3]
[get_ports APP_LED4]
LVCMOS18 [get_ports APP_LED4]
[get_ports APP_LED5]
LVCMOS18 [get_ports APP_LED5]
[get_ports APP_LED6]
LVCMOS18 [get_ports APP_LED6]
[get_ports APP_LED7]
LVCMOS18 [get_ports APP_LED7]
[get_ports APP_LED8]
LVCMOS18 [get_ports APP_LED8]
[get_ports DUT_I2C_SCL]
LVCMOS18 [get_ports DUT_I2C_SCL]
[get_ports DUT_I2C_SDA]
LVCMOS18 [get_ports DUT_I2C_SDA]
[get_ports DUT_PMB_ALERT]
LVCMOS18 [get_ports DUT_PMB_ALERT]
[get_ports DUT_PMB_CTRL]
LVCMOS18 [get_ports DUT_PMB_CTRL]
[get_ports DUT_PMB_CLK]
LVCMOS18 [get_ports DUT_PMB_CLK]
[get_ports DUT_PMB_DATA]
LVCMOS18 [get_ports DUT_PMB_DATA]
[get_ports USB_GPIO_0]
LVCMOS18 [get_ports USB_GPIO_0]
[get_ports USB_GPIO_1]
LVCMOS18 [get_ports USB_GPIO_1]
[get_ports USB_GPIO_2]
LVCMOS18 [get_ports USB_GPIO_2]
[get_ports USB_GPIO_3]
LVCMOS18 [get_ports USB_GPIO_3]
[get_ports USB_TXD_0]
LVCMOS18 [get_ports USB_TXD_0]
[get_ports USB_RXD_I]
LVCMOS18 [get_ports USB_RXD_I]
[get_ports USB_RTS_0_B]
LVCMOS18 [get_ports USB_RTS_0_B]
[get_ports USB_CTS_I_B]
LVCMOS18 [get_ports USB_CTS_I_B]
[get_ports SA2_SDHOST_D0]
LVCMOS18 [get_ports SA2_SDHOST_D0]
[get_ports SA2_SDHOST_D1]
LVCMOS18 [get_ports SA2_SDHOST_D1]
[get_ports SA2_SDHOST_D3]
LVCMOS18 [get_ports SA2_SDHOST_D3]
[get_ports SA2_SDHOST_D2]
LVCMOS18 [get_ports SA2_SDHOST_D2]
[get_ports SA2_SDHOST_CMD]
LVCMOS18 [get_ports SA2_SDHOST_CMD]
[get_ports SA2_SDHOST_CLK]
LVCMOS18 [get_ports SA2_SDHOST_CLK]
[get_ports MGT_MOD_SPI_SCK]
LVCMOS18 [get_ports MGT_MOD_SPI_SCK]
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015

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