Xilinx Virtex-7 VC7222 User Manual page 24

Chapter 1: VC7222 Board Features and Operation
User DIP Switches (Active High) and I/O Header
Callout 32,
The DIP switch SW2 provides a set of eight active-High switches that are connected to user
I/O pins on the FPGA as shown in
any other purpose determined by the user. Six of the eight I/Os also map to 2 x 6 test
header J125 providing external access for these pins (callout 33,
Table 1-11: User DIP Switches
Pin Function
AD26 User switch
AE26 User switch
AC26 User switch
AC27 User switch
AE27 User switch
AF27 User switch
AG27 User switch
AH27 User switch
Figure 1-14
X-Ref Target - Figure 1-14
User Pushbuttons (Active High)
Callout 31,
SW4 and SW5 are active-High user pushbuttons that are connected to user I/O pins on the
FPGA as shown in
the user.
Table 1-12: User Pushbuttons
Pin Function
AL22 User pushbutton
AM22 User pushbutton
24
Send Feedback
Figure 1-2.
FPGA (U1)
Direction IOSTANDARD
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Shows the user test I/O connector J125 (Callout 26,
Figure 1-2.
Table 1-12. These switches can be used for any purpose determined by
FPGA (U1)
Direction
Input
Input
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Table 1-11. These pins can be used to set control pins or
Schematic
Net Name
USER_SW1
USER_SW2
USER_SW3
USER_SW4
USER_SW5
USER_SW6
USER_SW7
USER_SW8
J125
1 2 USER_SW1
3 4 USER_SW2
5 6
USER_SW3
7 8 USER_SW4
9 10 USER_SW5
11 12 USER_SW6
GND
UG965_c1_14_070313
Figure 1-14: User Test I/O
Schematic
Net Name
IOSTANDARD
LVCMOS18 USER_PB1
LVCMOS18 USER_PB2
VC7222 Transceiver Characterization Board
Figure 1-2.).
SW2 DIP J125 Test
Switch Pin Header Pin
1 2
2 4
3 6
4 8
5 10
6 12
7 -
8 -
Figure 1-2).
Reference Designator
SW5
SW4
UG965 (v1.4) February 11, 2015