Xilinx Virtex-7 VC7222 User Manual page 50
Fpga gth and gtz transceiver characterization board
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Also See for Virtex-7 VC7222:
- Getting started manual (74 pages) ,
- Getting started manual (47 pages) ,
- Getting started manual (44 pages)
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Appendix C: Master Constraints File Listing
50
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set_property IOSTANDARD
set_property PACKAGE_PIN AJ14
set_property IOSTANDARD
#FMC2
set_property PACKAGE_PIN AN34
set_property IOSTANDARD
set_property PACKAGE_PIN AH31
set_property IOSTANDARD
set_property PACKAGE_PIN AJ31
set_property IOSTANDARD
set_property PACKAGE_PIN AK33
set_property IOSTANDARD
set_property PACKAGE_PIN AL33
set_property IOSTANDARD
#FMC2 LA
set_property PACKAGE_PIN AK32
set_property IOSTANDARD
set_property PACKAGE_PIN AL32
set_property IOSTANDARD
set_property PACKAGE_PIN AK30
set_property IOSTANDARD
set_property PACKAGE_PIN AK31
set_property IOSTANDARD
set_property PACKAGE_PIN AE28
set_property IOSTANDARD
set_property PACKAGE_PIN AF28
set_property IOSTANDARD
set_property PACKAGE_PIN AJ29
set_property IOSTANDARD
set_property PACKAGE_PIN AJ30
set_property IOSTANDARD
set_property PACKAGE_PIN AF29
set_property IOSTANDARD
set_property PACKAGE_PIN AG29
set_property IOSTANDARD
set_property PACKAGE_PIN AH28
set_property IOSTANDARD
set_property PACKAGE_PIN AH29
set_property IOSTANDARD
set_property PACKAGE_PIN AJ28
set_property IOSTANDARD
set_property PACKAGE_PIN AK28
set_property IOSTANDARD
set_property PACKAGE_PIN AL28
set_property IOSTANDARD
set_property PACKAGE_PIN AL29
set_property IOSTANDARD
set_property PACKAGE_PIN AF30
set_property IOSTANDARD
set_property PACKAGE_PIN AG30
set_property IOSTANDARD
set_property PACKAGE_PIN AG31
set_property IOSTANDARD
set_property PACKAGE_PIN AG32
set_property IOSTANDARD
set_property PACKAGE_PIN AH32
set_property IOSTANDARD
set_property PACKAGE_PIN AH33
set_property IOSTANDARD
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LVCMOS18 [get_ports FMC1_LA33_P]
[get_ports FMC1_LA33_N]
LVCMOS18 [get_ports FMC1_LA33_N]
[get_ports FMC2_PRSNT_M2C_L]
LVCMOS18 [get_ports FMC2_PRSNT_M2C_L]
[get_ports FMC2_CLK0_M2C_P]
LVCMOS18 [get_ports FMC2_CLK0_M2C_P]
[get_ports IO_L11N_T1_SRCC_14]
LVCMOS18 [get_ports IO_L11N_T1_SRCC_14]
[get_ports FMC2_CLK1_M2C_P]
LVCMOS18 [get_ports FMC2_CLK1_M2C_P]
[get_ports FMC2_CLK1_M2C_N]
LVCMOS18 [get_ports FMC2_CLK1_M2C_N]
[get_ports FMC2_LA00_CC_P]
LVDS
[get_ports FMC2_LA00_CC_P]
[get_ports FMC2_LA00_CC_N]
LVDS
[get_ports FMC2_LA00_CC_N]
[get_ports FMC2_LA01_CC_P]
LVCMOS18 [get_ports FMC2_LA01_CC_P]
[get_ports FMC2_LA01_CC_N]
LVCMOS18 [get_ports FMC2_LA01_CC_N]
[get_ports FMC2_LA02_P]
LVCMOS18 [get_ports FMC2_LA02_P]
[get_ports FMC2_LA02_N]
LVCMOS18 [get_ports FMC2_LA02_N]
[get_ports FMC2_LA03_P]
LVCMOS18 [get_ports FMC2_LA03_P]
[get_ports FMC2_LA03_N]
LVCMOS18 [get_ports FMC2_LA03_N]
[get_ports FMC2_LA04_P]
LVCMOS18 [get_ports FMC2_LA04_P]
[get_ports FMC2_LA04_N]
LVCMOS18 [get_ports FMC2_LA04_N]
[get_ports FMC2_LA05_P]
LVCMOS18 [get_ports FMC2_LA05_P]
[get_ports FMC2_LA05_N]
LVCMOS18 [get_ports FMC2_LA05_N]
[get_ports FMC2_LA06_P]
LVCMOS18 [get_ports FMC2_LA06_P]
[get_ports FMC2_LA06_N]
LVCMOS18 [get_ports FMC2_LA06_N]
[get_ports FMC2_LA07_P]
LVCMOS18 [get_ports FMC2_LA07_P]
[get_ports FMC2_LA07_N]
LVCMOS18 [get_ports FMC2_LA07_N]
[get_ports FMC2_LA08_P]
LVCMOS18 [get_ports FMC2_LA08_P]
[get_ports FMC2_LA08_N]
LVCMOS18 [get_ports FMC2_LA08_N]
[get_ports FMC2_LA09_P]
LVCMOS18 [get_ports FMC2_LA09_P]
[get_ports FMC2_LA09_N]
LVCMOS18 [get_ports FMC2_LA09_N]
[get_ports FMC2_LA10_N]
LVCMOS18 [get_ports FMC2_LA10_N]
[get_ports FMC2_LA10_N]
LVCMOS18 [get_ports FMC2_LA10_N]
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
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