Xilinx Virtex-7 VC7222 User Manual page 34

Chapter 1: VC7222 Board Features and Operation
USB-to-UART Bridge
Callout 28,
A USB-to-UART bridge (U34, Silicon Laboratories CP2103) is provided for serial
communication between a host computer and the FPGA over a USB cable. The USB
connector on the board is a mini-B receptacle (J79) and its pinout is shown in
Table 1-17: USB Mini-B Receptacle Pin Assignments and Signals
J79 Pin
The CP2103 supports an IO voltage range of 1.8V to 3.3V. Xilinx UART IP is expected to be
implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four
signal pins:
•
•
•
•
Connections of these signals between the FPGA and the CP2103 are listed in
Table 1-18: FPGA to UART Connections
The bridge device also provides as many as 4 GPIO signals that can be defined by the user
for status and control information
Table 1-19: CP2103 USB-to-UART Bridge User GPIO
34
Send Feedback
Figure 1-2.
Signal Name
1 VBUS
2 USB_DATA_N
3 USB_DATA_P
4 GROUND
Transmit (TX)
Receive (RX)
Request to Send (RTS)
Clear to Send (CTS)
FPGA (U1)
Pin Function Direction IOSTANDARD
AG11 RTS Output
AL9 CTS Input
AL10 TX Output
AK10 RX Input
FPGA (U1)
Pin Function Direction IOSTANDARD
AD10 SelectIO In/Out
AC8 SelectIO In/Out
AD8 SelectIO In/Out
AK11 SelectIO In/Out
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Description
+5V into the CP2103 USB-to-UART bridge at U34.
Used to sense USB network connection.
Bidirectional differential serial data (N-side).
Bidirectional differential serial data (P-side).
Signal ground.
Schematic
Net Name
LVCMOS18 USB_CTS_I_B
LVCMOS18 USB_RTS_0_B
LVCMOS18 USB_RXD_I
LVCMOS18 USB_TXD_0
(Table 1-19).
Schematic
Net Name
LVCMOS18 USB_GPIO_0
LVCMOS18 USB_GPIO_1
LVCMOS18 USB_GPIO_2
LVCMOS18 USB_GPIO_3
VC7222 Transceiver Characterization Board
Table 1-17.
Table 1-18.
Device (U34)
Pin Function Direction
22 CTS Input
23 RTS Output
24 RXD Input
25 TXD Output
Device (U34)
Pin Function Direction
19 GPIO In/Out
18 GPIO In/Out
17 GPIO In/Out
16 GPIO In/Out
UG965 (v1.4) February 11, 2015