Xilinx Virtex-7 VC7222 User Manual page 22

Chapter 1: VC7222 Board Features and Operation
Table 1-9: SuperClock-2 FPGA I/O Mapping
FPGA (U1)
Pin Function
AK8 Clock recovery
AL8 Clock recovery
AE6 Clock recovery
AF5 Clock recovery
AG1 Clock recovery
AH1 Clock recovery
AJ11 Regional clock
AJ10 Regional clock
AF8 Control I/O
AH9 Control I/O
AH8 Control I/O
AJ9 Control I/O
AJ8 Control I/O
AM10 Control I/O
AM9 Control I/O
AF12 Control I/O
AF9 Control I/O
AG9 Control I/O
AG12 Control I/O
AH12 Control I/O
AP10 Control I/O
AP9 Control I/O
AK12 Control I/O
AL12 Control I/O
AN12 Control I/O
AN11 Control I/O
AN9 Control I/O
22
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Direction IOSTANDARD
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Output LVDS
Output LVDS
Input LVDS
Input LVDS
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
Output LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Output LVCMOS18
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Schematic
Net Name
Pin
CM_LVDS1_P 1 Clock recovery
CM_LVDS1_N 3 Clock recovery
CM_LVDS2_P 9 Clock recovery
CM_LVDS2_N 11 Clock recovery
CM_LVDS3_P 17 Clock recovery
CM_LVDS3_N 19 Clock recovery
CM_GCLK_P 25
CM_GCLK_N 27
CM_CTRL_0 61
CM_CTRL_1 63
CM_CTRL_2 65
CM_CTRL_3 67
CM_CTRL_4 69
CM_CTRL_5 71
CM_CTRL_6 73
CM_CTRL_7 75
CM_CTRL_8 77
CM_CTRL_9 79
CM_CTRL_10 81
CM_CTRL_11 83
CM_CTRL_12 85
CM_CTRL_13 87
CM_CTRL_14 89
CM_CTRL_15 91
CM_CTRL_16 93
CM_CTRL_17 95
CM_CTRL_18 97
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
J82 Pin
Function Direction
Output
Output
Output
Output
Input
Input
Global clock Output
Global clock Output
NC -
NC -
NC -
DEC Input
INC Input
ALIGN Input
NC -
NC -
NC -
LOL
INT_ALRM Input
C1B Input
C2B Input
C3B Input
C1A Input
C2A Input
NC -
CS0_C3A Input
CS1_C4A Input