Xilinx Virtex-7 VC7222 User Manual page 23

Table 1-9: SuperClock-2 FPGA I/O Mapping (Cont'd)
FPGA (U1)
Pin Function
AN8 Control I/O
AN13 Control I/O
AP13 Control I/O
AM12 Control I/O
AM11 Control I/O
AE8 CM_RESET
User LEDs (Active High)
Callout 30,
DS13 through DS20 are eight active-High LEDs that are connected to user I/O pins on the
FPGA as shown in
purpose determined by the user.
Table 1-10: User LEDs
Pin Function
AH26 User LED
AJ26 User LED
AM25 User LED
AM26 User LED
AN26 User LED
AP26 User LED
AM24 User LED
AN24 User LED
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
Direction IOSTANDARD
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Figure 1-2.
Table 1-10 These LEDs can be used to indicate status or any other
FPGA (U1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
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Schematic
Net Name
Pin
CM_CTRL_19 99
CM_CTRL_20 101
CM_CTRL_21 103
CM_CTRL_22 105
CM_CTRL_23 107
CM_RST 66
Schematic Net
Name
IOSTANDARD
LVCMOS18 APP_LED1
LVCMOS18 APP_LED2
LVCMOS18 APP_LED3
LVCMOS18 APP_LED4
LVCMOS18 APP_LED5
LVCMOS18 APP_LED6
LVCMOS18 APP_LED7
LVCMOS18 APP_LED8
Detailed Description
J82 Pin
Function Direction
NC -
NC -
NC -
NC -
NC -
RESET_B Input
Reference
Designator
DS19
DS20
DS17
DS18
DS16
DS15
DS13
DS14
23
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