Xilinx Virtex-7 VC7222 User Manual page 54

Fpga gth and gtz transceiver characterization board
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Appendix C: Master Constraints File Listing
54
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set_property IOSTANDARD
set_property PACKAGE_PIN AN28
set_property IOSTANDARD
set_property PACKAGE_PIN AP28
set_property IOSTANDARD
set_property PACKAGE_PIN AG25
set_property IOSTANDARD
set_property PACKAGE_PIN AG26
set_property IOSTANDARD
#SuperClock2_MODULE
set_property PACKAGE_PIN AE8
set_property IOSTANDARD
set_property PACKAGE_PIN AF8
set_property IOSTANDARD
set_property PACKAGE_PIN AH9
set_property IOSTANDARD
set_property PACKAGE_PIN AH8
set_property IOSTANDARD
set_property PACKAGE_PIN AJ9
set_property IOSTANDARD
set_property PACKAGE_PIN AJ8
set_property IOSTANDARD
set_property PACKAGE_PIN AM10
set_property IOSTANDARD
set_property PACKAGE_PIN AM9
set_property IOSTANDARD
set_property PACKAGE_PIN AF12
set_property IOSTANDARD
set_property PACKAGE_PIN AF9
set_property IOSTANDARD
set_property PACKAGE_PIN AG9
set_property IOSTANDARD
set_property PACKAGE_PIN AG12
set_property IOSTANDARD
set_property PACKAGE_PIN AH12
set_property IOSTANDARD
set_property PACKAGE_PIN AP10
set_property IOSTANDARD
set_property PACKAGE_PIN AP9
set_property IOSTANDARD
set_property PACKAGE_PIN AK12
set_property IOSTANDARD
set_property PACKAGE_PIN AL12
set_property IOSTANDARD
set_property PACKAGE_PIN AN12
set_property IOSTANDARD
set_property PACKAGE_PIN AN11
set_property IOSTANDARD
set_property PACKAGE_PIN AN9
set_property IOSTANDARD
set_property PACKAGE_PIN AN8
set_property IOSTANDARD
set_property PACKAGE_PIN AN13
set_property IOSTANDARD
set_property PACKAGE_PIN AP13
set_property IOSTANDARD
set_property PACKAGE_PIN AM12
set_property IOSTANDARD
set_property PACKAGE_PIN AM11
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LVCMOS18 [get_ports FMC2_HB08_N]
[get_ports FMC2_HB09_P]
LVCMOS18 [get_ports FMC2_HB09_P]
[get_ports FMC2_HB09_N]
LVCMOS18 [get_ports FMC2_HB09_N]
[get_ports FMC2_HB17_CC_P]
LVCMOS18 [get_ports FMC2_HB17_CC_P]
[get_ports FMC2_HB17_CC_N]
LVCMOS18 [get_ports FMC2_HB17_CC_N]
[get_ports CM_RST]
LVCMOS18 [get_ports CM_RST]
[get_ports CM_CTRL_0]
LVCMOS18 [get_ports CM_CTRL_0]
[get_ports CM_CTRL_1]
LVCMOS18 [get_ports CM_CTRL_1]
[get_ports CM_CTRL_2]
LVCMOS18 [get_ports CM_CTRL_2]
[get_ports CM_CTRL_3]
LVCMOS18 [get_ports CM_CTRL_3]
[get_ports CM_CTRL_4]
LVCMOS18 [get_ports CM_CTRL_4]
[get_ports CM_CTRL_5]
LVCMOS18 [get_ports CM_CTRL_5]
[get_ports CM_CTRL_6]
LVCMOS18 [get_ports CM_CTRL_6]
[get_ports CM_CTRL_7]
LVCMOS18 [get_ports CM_CTRL_7]
[get_ports CM_CTRL_8]
LVCMOS18 [get_ports CM_CTRL_8]
[get_ports CM_CTRL_9]
LVCMOS18 [get_ports CM_CTRL_9]
[get_ports CM_CTRL_10]
LVCMOS18 [get_ports CM_CTRL_10]
[get_ports CM_CTRL_11]
LVCMOS18 [get_ports CM_CTRL_11]
[get_ports CM_CTRL_12]
LVCMOS18 [get_ports CM_CTRL_12]
[get_ports CM_CTRL_13]
LVCMOS18 [get_ports CM_CTRL_13]
[get_ports CM_CTRL_14]
LVCMOS18 [get_ports CM_CTRL_14]
[get_ports CM_CTRL_15]
LVCMOS18 [get_ports CM_CTRL_15]
[get_ports CM_CTRL_16]
LVCMOS18 [get_ports CM_CTRL_16]
[get_ports CM_CTRL_17]
LVCMOS18 [get_ports CM_CTRL_17]
[get_ports CM_CTRL_18]
LVCMOS18 [get_ports CM_CTRL_18]
[get_ports CM_CTRL_19]
LVCMOS18 [get_ports CM_CTRL_19]
[get_ports CM_CTRL_20]
LVCMOS18 [get_ports CM_CTRL_20]
[get_ports CM_CTRL_21]
LVCMOS18 [get_ports CM_CTRL_21]
[get_ports CM_CTRL_22]
LVCMOS18 [get_ports CM_CTRL_22]
[get_ports CM_CTRL_23]
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015

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