Xilinx Virtex-7 VC7222 User Manual page 21

200 MHz 2.5V LVDS Oscillator
U35 (callout 15,
The VC7222 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region
clock capable (MRCC) inputs on the FPGA.
LVDS oscillator.
Table 1-7
Table 1-7: LVDS Oscillator MRCC Connections
FPGA (U1)
Pin Function
AL24 SYSTEM CLOCK_P
AL25 SYSTEM CLOCK_N
Differential SMA MRCC Pin Inputs
Callout 36,
The VC7222 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA MRCC pins are
connected to the SMA connectors as shown in
Table 1-8: Differential SMA Clock Connections
Pin Function
AK32 USER CLOCK_1_P
AL32 USER CLOCK_1_N
AK3 USER CLOCK_2_P
AL3 USER CLOCK_2_N
SuperClock-2 Module
Callout 14,
The SuperClock-2 module connects to the clock module interface connector (J82) and
provides a programmable, low-noise and low-jitter clock source for the VC7222 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin.
interface. The VC7222 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and
VCCO_HP input power to the clock module interface.
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
Figure 1-2).
Direction IOSTANDARD
Input LVDS
Input LVDS
Figure 1-2.
FPGA (U1)
Direction IOSTANDARD
Input
Input
Input
Input
Figure 1-2.
Table 1-9
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Table 1-7 lists the FPGA pin connections to the
Schematic
Net Name
Pin
LVDS_OSC_P 4 200 MHz LVDS oscillator
LVDS_OSC_N 5 201 MHz LVDS oscillator
Table 1-8.
Schematic Net Name
LVDS CLK_DIFF_1_P
LVDS CLK_DIFF_1_N
LVDS CLK_DIFF_2_P
LVDS CLK_DIFF_2_N
shows the FPGA I/O mapping for the SuperClock-2 module
Detailed Description
Device (U35)
Function Direction
Output
Output
SMA Connector
J99
J100
J98
J101
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