Xilinx Virtex-7 VC7222 User Manual page 33

Table 1-15: GTZ Transceiver Pins (Cont'd)
Information for each GTZ transceiver clock input is shown in
Table 1-16:
VC7222 Transceiver Characterization Board
UG965 (v1.4) February 11, 2015
FPGA (U1) Pin Net Name
A25 300_TX3_P
A24 300_TX3_N
A19 300_RX3_P
A18 300_RX3_N
C17 300_TX4_P
C16 300_TX4_N
C11 300_RX4_P
C10 300_RX4_N
A16 300_TX5_P
A15 300_TX5_N
A10 300_RX5_P
A9 300_RX5_N
C14 300_TX6_P
C13 300_TX6_N
C8 300_RX6_P
C7 300_RX6_N
A13 300_TX7_P
A12 300_TX7_N
A7 300_RX7_P
A6 300_RX7_N
GTZ Transceiver Reference Clock Inputs
FPGA (U1) Pin Net Name
E17 300_REFCLK0_P
E16 300_REFCLK0_N
E21 300_REFCLK1_P
E20 300_REFCLK1_N
www.xilinx.com
Detailed Description
Octal Connector
300A J25
300A J25
300A J25
300A J25
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
300B J18
Table 1-16.
SMA Connector
J57
J56
J46
J47
Send Feedback
Trace Length
(mils)
2,540
2,540
2,696
2,696
2,738
2,737
2,776
2,776
2,412
2,412
2,181
2,181
2,646
2,645
2,311
2,311
2,844
2,844
2,839
2,839
33