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6.3
Control function
The Model 7001 is controlled by two internal micropro-
cessors. The primary controller resides on the digital
board, and is responsible for supervising the overall
operation of the Model 7001. The secondary controller
is located on the display board and is primarily respon-
sible for supervising operation of the display and key-
board and communicating with the main processor.
The primary controller consists of the following com-
ponents:
•
68302 16-bit microprocessor
•
16MHz oscillator
•
Power-up reset circuitry
128K × 16-bit EPROM
•
Two 32K × 8-bit RAM with battery backup
•
2K × 8-bit EEPROM
•
The display microcontroller and associated compo-
nents consist of the following:
•
68705 8-bit microcontroller
•
5812 and 5818 source drivers
6.3.1 Reset circuitry
For the following discussion, also refer to digital board
schematic 7001-106.
Voltage supervision and monitoring is provided by a
7770-5 (U102) which checks for under-voltage condi-
tions. On power-up, as Vcc approaches +1V, 1RESET is
active low. As Vcc approaches +3.5V, the time delay cir-
cuit of the 7770-5 activates, keeping 1RESET low for an
additional 200msec. When capacitor C146 (10 µ F) fully
charges, 1RESET then goes high. If Vcc falls below
4.55V, 1RESET is reasserted low, and remains low until
Vcc again exceeds 4.6V, and after the time delay has
timed out.
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1RESET is an open collector output which is tied to Vcc
through a 470 Ω resistor (R121). 1RESET is tied to the
RESET and HALT pins of the 68302 processor, each
through a 560 Ω resistor (R130 and R131). These two re-
sistors enable the 68302 main processor to activate a re-
set condition in addition to when Vcc falls below 4.55V.
6.3.2 Address decoding
Address decoding is performed internally by the 68302
processor. No additional circuitry is required for this
function.
6.3.3 Memory
For the following discussion, also refer to digital board
schematic 7001-106.
The Model 7001's operating software is stored in U113,
a 27C220 (128K × 16-bit) EPROM memory. The revision
level of the software is displayed by the instrument
upon power-up.
During system operation, relay setups, scan lists, for-
bidden channels, and other temporary storage tasks
are accomplished through U110 and U111, which are
32K-byte static CMOS RAM chips. Power source and
chip enable lines are routed through U108, a DS-1210
NVRAM controller. Figure 6-2 includes a simplified
schematic of the RAM and battery back-up circuitry.
The NVRAM controller performs the functions of
switching the RAM power source between Vcc and the
lithium memory back-up battery BT100. It also dis-
ables the chip enable (CE) to the RAM when Vcc is out-
side the specified limits (see the previous information
describing the reset circuitry).
If battery power drops below a specified limit while
Vcc is not present, the DS-1210 chip (U108) disables the
chip enable to the RAM after Vcc is restored. Then the
CPU tries to read a special pattern in the RAM. If the
CPU detects errors, it overrides the pattern and places
the mainframe in a known state.
Theory of Operation
6-3
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