Trigger Event Status - Keithley 7001 Instruction Manual

ANDed with the bits of the Sequence Event Enable Register
and applied to an OR gate. The output of the OR gate is ap-
plied to bit B1 of the Arm Condition Register (see paragraph
5.6.3). The following SCPI query command can be used to
read the Sequence Event Register:
:STATus:OPERation:ARM:SEQuence?
Reading this register using the above SCPI command clears
the register. The following list summarizes all operations that
will clear the Sequence Event Register:
1. Cycling power.
2. Sending the *CLS common command.
3. Sending the :STATus:OPERation:ARM:SEQuence?
query command.
Sequence Event Enable Register — This register is pro-
grammed by the user and serves as a mask for the Sequence
Event Register. When masked, a set bit in the Sequence
Event Register will not set bit B1 of the Arm Condition Reg-
ister. Conversely, when unmasked, a set bit in the Sequence
Event Register will set the bit B1 of the Arm Condition Reg-
ister.
A bit in the Sequence Event Register is masked when the
corresponding bit in the Sequence Event Enable Register is
cleared (0). When the masked bit of the Sequence Event Reg-
ister sets, it is ANDed with the corresponding cleared bit in
the Sequence Event Enable Register. The logic "0" output of
the AND gate is applied to the input of the OR gate and thus,
will not set bit B1 of the Arm Condition Register.
A bit in the Sequence Event Register is unmasked when the
corresponding bit in the Sequence Event Enable Register is
set (1). When the unmasked bit of the Sequence Event Reg-
ister sets, it is ANDed with the corresponding set bit in the
Sequence Event Enable Register. The logic "1" output of the
AND gate is applied to the input of the OR gate and thus, will
set bit B1 of the Arm Condition Register.
The individual bits of the Sequence Event Enable Register
can be set or cleared by using the following SCPI command:
:STATus:OPERation:ARM:SEQuence:ENABle <NRf>
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The following SCPI query command can be used to read the
Sequence Event Enable Register:
:STATus:OPERation:ARM:SEQuence:ENABle?
Reading this register using the above SCPI command will
not clear the register. The following list summarizes opera-
tions that will clear the Sequence Event Enable Register:
1. Cycling power.
2. Sending the :STATus:OPERation:ARM:SEQuence:EN-
ABle 0 command.

5.6.5 Trigger event status

The reporting of the trigger event is controlled by a set of 16-
bit registers; the Trigger Condition Register, the Transition
Filter, the Trigger Event Register, and the Trigger Event En-
able Register. Figure 5-10 shows how these registers are
structured.
Bit B1 (Seq1) of the register set is used for the trigger event
(In Trigger Layer). In general, Bit B1 sets when the instru-
ment is in (or has exited) the measure layer of operation. An
explanation of the Model 7001 operation process is provided
in paragraph 5.7. The various registers used for trigger event
status are described as follows: Note that these registers are
controlled by the :STATus:OPERation:TRIGger commands
of the :STATus subsystem (see paragraph 5.16).
Trigger Condition Register — This is a real-time 16-bit
read-only register that constantly updates to reflect the trig-
ger layer status of the instrument. If bit B1 is set, the instru-
ment is in the trigger layer (measure layer) of operation.
The following SCPI query command can be used to read the
Trigger Condition Register:
:STATus:OPERation:TRIGger:CONDition?
The Trigger Condition Register and the Transition Filter are
used to set bit B1 of the Trigger Event Register. The Transi-
tion Filter is discussed next.
IEEE-488 Reference
5-15