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IEEE-488 Reference
5.6.6 Questionable event status
The Model 7001 does not implement questionable events.
Thus, the QSB summary bit is always zero as shown in Fig-
ure 5-5. Even though they are not used, the questionable
event registers are part of the status structure as required by
SCPI.
5.6.7 Queues
The Model 7001 uses two queues; the Output Queue and the
Error/Status Queue. The queues are first-in first-out (FIFO)
registers. They are used to hold data messages and error/sta-
tus messages respectively. The Model 7001 Status Model
(Figure 5-5) shows how the two queues are structured with
the other registers.
Output Queue The Output Queue is used to hold all data
that pertains to the normal operation of the instrument. For
example, when a query command is sent, the data message
that pertains to that query is placed in the Output Queue.
When a data message is placed in the Output Queue, the
Message Available (MAV) bit in the Status Byte Register be-
comes set. A data message is cleared from the Output Queue
when it is read. The Output Queue is considered cleared
when it is empty. An empty Output Queue clears the MAV
bit in the Status Byte Register.
A message from the Output Queue is read by addressing the
Model 7001 to talk. The following programming example in
HP BASIC 4.0 sends a query command, sends the data mes-
sage to the computer, and then displays it on the CRT.
10 OUTPUT 707; "*IDN?"
20 ENTER 707; A$
30 PRINT A$
40 END
Error Queue The Error Queue is used to hold error mes-
sages and status messages. When an error or status event oc-
curs, a message that defines the error/status is placed in the
Error Queue. This queue will hold up to 10 messages.
5-18
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! Request
identification
code
! Address 7001 to talk
! Display ID code
When a message is placed in the Error Queue, the Error
Available (EAV) bit in the Status Byte Register is set. An er-
ror message is cleared from the Error Queue when it is read.
The Error Queue is considered cleared when it is empty. An
empty Error Queue clears the EAV bit in the Status Byte
Register.
An error message from the Error Queue is read by sending
either of the following SCPI query commands and then ad-
dressing the Model 7001 to talk:
:SYSTem:ERRor?
:STATus:QUEue?
Refer to paragraphs 5.16.7 (:STATus:QUEue?) and 5.17.4
(:SYSTem:ERRor?) for complete information on reading er-
ror messages.
5.6.8 Status byte and service request (SRQ)
Service request is controlled by two 8-bit registers; the Status
Byte Register and the Service Request Enable Register. The
structure of these registers is shown in Figure 5-11.
Status Byte Register — The summary messages from the
status registers and queues are used to set or clear the appro-
priate bits (B2, B3, B4, B5 and B7) of the Status Byte Reg-
ister. These bits do not latch and their states (0 or 1) are solely
dependent on the summary messages (0 or 1). For example,
if the Standard Event Status Register is read, its register will
clear. As a result, its summary message will reset to 0, which
in turn will clear the ESB bit in the Status Byte Register.
Bit B6 in the Status Byte Register is either:
• The Master Summary Status (MSB) bit, sent in re-
sponse to the *STB? command, indicates the status
of any set bits with corresponding enable bits set.
• The Request for Service (RQS) bit, sent in response
to a serial poll, indicates which device was request-
ing service by pulling on the SRQ line.
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